RTL engineer

[RTL] SDF File Analysis

In the previous article, we discussed that Post-Simulation (GLS) is essential to ensure the actual chip operation.

In the previous article, we discussed how semiconductor process uncertainty (process variation) changes the speed of transistors, and…

RTL engineer

As an RTL engineer, when I run synthesis or do STA (Static Timing Analysis), I come across PVT…

Verilog

In the last post, while designing the UART Rx module, I was looking at the asynchronous signal (Rx) coming from the outside…

Verilog

In Verilog, ports are connected with wires to communicate between modules. In System Verilog…

Verilog

Related article ✅[System Verilog] Overview – 1 introduction, data type…