Hardware Optimization - Float to Integer
Designing NPU (Neural Processing Unit) architectures at a low-power AI semiconductor startup constantly reminds me of a harsh truth:
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Vivado Troubleshooting - Preventing Pruning and Solving Tool Crashes
When designing an NPU for low-power AI semiconductor edge devices, you often find yourself spending more time fighting the EDA tools than writing actual RTL.
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FPGA Practical Design - The Ultimate Guide to BRAM Initialization
When mapping a low-power AI semiconductor architecture onto an FPGA, one of the very first hurdles you encounter is 'Memory Design'.
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[RTL] Multi-Vt and Doping: Same Gate, Different Speeds
When an RTL engineer analyzes the synthesis results, he or she may find that the same AND2 gate has a subtly different name.
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[Semiconductor Metrology] Measuring the Thickness of Invisible Films: Ellipsometry and Alpha Step
When manufacturing semiconductor chips, we say, "We deposited 5nm of HfO2."
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AI Architecture 15. The Heart of Systolic Array
The Von Neumann architecture, the origin of modern computing, separates the 'Processing Unit (CPU)' from the 'Storage Unit (Memory)'.
