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The story of a non-major becoming an RTL engineer
  • AI & HW Fundamentals

    AI Architecture 11. Depthwise Separable Conv: The MobileNet Paradox

    In the previous 3 Mappings of Conv Operations, we looked at a strategy to sacrifice memory and gain computational speed (GEMM) through the Im2Col method when processing standard convolutions in hardware.

  • Zero Padding
    AI & HW Fundamentals

    AI Architecture 10. Padding and Pooling Hardware Issues

    In the previous 3 Mappings of Conv Operations, we explored the massive trade-off (like Im2Col) of exchanging memory ...

  • AI & HW Fundamentals

    AI Architecture 9. Three Mappings of Conv Operations: Direct vs. Im2Col vs. Winograd

    In the previous post, we learned that hardware loves CNNs (Convolutional Neural Networks) because of Locality and Data Reuse. Theoretically, CNNs seem like the perfect hardware-friendly algorithm.

  • Kernel sliding
    AI & HW Fundamentals

    AI Architecture 8. CNN and Locality

    In the previous post, we confirmed how inefficient MLP (Fully Connected Layer) is from a hardware perspective. Due to its structure of fetching a weight once,

  • The Memory Wall
    AI & HW Fundamentals

    AI Architecture 7. MLP and the Memory Wall

    In previous posts, we learned about Quantization techniques to shave down data size to reduce hardware costs. So, why do we try so desperately to reduce data size?

  • Quantization
    AI & HW Fundamentals

    AI Architecture 6. INT8 Quantization Basics

    In the previous post, we examined how differences in Number Formats affect hardware area and power consumption. We established that FP32 ...

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