[Verilog] FSM (Finite State Machine) RTL Design Principles
모든 디지털 시스템은 크게 데이터를 처리하는 Data Path와 이를 지휘하는…
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[RTL] RTL Arithmetic: Bit Extension, Saturation Operations, and Rounding
When designing RTL, you declare wire [7:0] a, b, c…
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[RTL] Fan-in and Fan-out: The Hidden Causes of Timing Issues and Solutions
When doing RTL design, it is functionally perfect, but timing is poor during the synthesis or P&R stages…
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[RTL] Low-Power RTL Design Techniques (Clock Gating)
What are the most important specifications for the latest mobile and IoT devices? Performance…
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[RTL] Asynchronous FIFO design
In the last RTL CDC article, we learned about synchronizing single-bit signals…
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[Verilog] Asynchronous Signal Processing: CDC and Metastability
In the last post, while designing the UART Rx module, I was looking at the asynchronous signal (Rx) coming from the outside…
![[Verilog] 비동기 신호 처리: CDC와 Metastability](data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%20727%20322'%3E%3C/svg%3E)