[RTL] Low-Power RTL Design Techniques (Clock Gating)
What are the most important specifications for the latest mobile and IoT devices? Performance…
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[RTL] Asynchronous FIFO design
In the last RTL CDC article, we learned about synchronizing single-bit signals…
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[Verilog] Asynchronous Signal Processing: CDC and Metastability
In the last post, while designing the UART Rx module, I was looking at the asynchronous signal (Rx) coming from the outside…
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[Verilog] UART RTL design 3
This article concludes the UART RTL design. Related article: ✅[Verilog] Simulation…
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[Verilog] UART RTL design 2
Continuing from the previous post, let's continue with the UART RTL design. Related posts…
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[Verilog] UART RTL design 1
This time, we'll design a simple communication IP, a Universal Asynchronous Receiver/Transmitter (UART). Related article…
![[Verilog] 비동기 신호 처리: CDC와 Metastability](data:image/svg+xml;base64,PHN2ZyB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciIHZpZXdCb3g9IjAgMCA3MjcgMzIyIiB3aWR0aD0iNzI3IiBoZWlnaHQ9IjMyMiIgYnYtaW1nLXVybD0iaHR0cHM6Ly9ydGxlYXJuZXIuY29tL3dwLWNvbnRlbnQvdXBsb2Fkcy9hbF9vcHRfY29udGVudC9JTUFHRS9ydGxlYXJuZXIuY29tL3dwLWNvbnRlbnQvdXBsb2Fkcy8yMDI1LzEyL2ltZy5qcGcuYnYud2VicCIgYnYtcmVzaXplZC1pbmZvcz0iTkRnd0xtcHdaem8wT0RBcU1qRXpPemd5TUM1cWNHYzZOekkzS2pNeU1qc3hOVE0yTG1wd1p6bzNNamNxTXpJeSI+PC9zdmc+)
![[Verilog] UART RTL design 2](data:image/svg+xml;base64,PHN2ZyB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciIHZpZXdCb3g9IjAgMCA3NjggMTI4OSIgd2lkdGg9Ijc2OCIgaGVpZ2h0PSIxMjg5IiBidi1pbWctdXJsPSJodHRwczovL3J0bGVhcm5lci5jb20vd3AtY29udGVudC91cGxvYWRzL2FsX29wdF9jb250ZW50L0lNQUdFL3J0bGVhcm5lci5jb20vd3AtY29udGVudC91cGxvYWRzLzIwMjQvMDgv6re466a8MS05LTc2OHgxMjg5LmpwZy5idi53ZWJwIiBidi1yZXNpemVkLWluZm9zPSJZblpmY21WemFYcGxaRjl0YjJKcGJHVXVhbkJuT2pRNE1DbzRNRFk3WW5aZmNtVnphWHBsWkY5cGNHRmtMbXB3WnpvM01ETXFNVEU0TUR0aWRsOXlaWE5wZW1Wa1gyUmxjMnQwYjNBdWFuQm5PamMyT0NveE1qZzUiPjwvc3ZnPg==)
