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RTLearner
The story of a non-major becoming an RTL engineer
  • 글 설명 이미지, Register setting
    Verilog

    [Verilog] Practice 2 – APB interface design

    Now, let's start designing the APB interface in earnest. Let's outline and verify the interface...

  • 글 설명 이미지, APB interface
    Verilog

    [Verilog] Practice 1 – APB interface intro, BFM

    Now, let's get into some practical Verilog. The goal is to understand what an APB interface is, and…

  • SoC integration
    RTL engineer

    RTL design engineer work

    During my master's degree, I conducted research on semiconductor processes and devices, but my job…

  • 글 설명 이미지, 인스턴스화
    Verilog

    [Verilog] Grammar 2 – Instantiation, Flip-Flops, and Latches

    Continuing from my last post, I'll explain Verilog grammar. Related articles…

  • 글 설명 이미지
    Verilog

    [Verilog] Grammar 1 – Basic Structure, Procedural Assignment, and Continuous Assignment

    In this article, we'll explore the basic syntax of Verilog. First, you need to know...

  • 글 설명 이미지, EDA playground
    Verilog

    [Verilog] Simulation Environment Settings (EDA Playground, Icarus Verilog)

    In this article, we will look at an overview of Verilog, one of the HDLs, and its simulation methods.

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