[RTL] Low-Power RTL Design Techniques (Clock Gating)
What are the most important specifications for the latest mobile and IoT devices? Performance…
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[RTL] Asynchronous FIFO design
In the last RTL CDC article, we learned about synchronizing single-bit signals…
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[RTL] SDF File Analysis
In the previous article, we discussed that Post-Simulation (GLS) is essential to ensure the actual chip operation.
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[RTL] RTL Simulation Isn't Perfect: Why do Post-Sim (GLS)?
In the previous article, we discussed how semiconductor process uncertainty (process variation) changes the speed of transistors, and…
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[RTL] Correlation Between Process Variation and Setup/Hold Time
As an RTL engineer, when I run synthesis or do STA (Static Timing Analysis), I come across PVT…
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[Verilog] Asynchronous Signal Processing: CDC and Metastability
In the last post, while designing the UART Rx module, I was looking at the asynchronous signal (Rx) coming from the outside…
![[Verilog] 비동기 신호 처리: CDC와 Metastability](data:image/svg+xml;base64,PHN2ZyB4bWxucz0iaHR0cDovL3d3dy53My5vcmcvMjAwMC9zdmciIHZpZXdCb3g9IjAgMCA3MjcgMzIyIiB3aWR0aD0iNzI3IiBoZWlnaHQ9IjMyMiIgYnYtaW1nLXVybD0iaHR0cHM6Ly9ydGxlYXJuZXIuY29tL3dwLWNvbnRlbnQvdXBsb2Fkcy9hbF9vcHRfY29udGVudC9JTUFHRS9ydGxlYXJuZXIuY29tL3dwLWNvbnRlbnQvdXBsb2Fkcy8yMDI1LzEyL2ltZy5qcGcuYnYud2VicCIgYnYtcmVzaXplZC1pbmZvcz0iTkRnd0xtcHdaem8wT0RBcU1qRXpPemd5TUM1cWNHYzZOekkzS2pNeU1qc3hOVE0yTG1wd1p6bzNNamNxTXpJeSI+PC9zdmc+)