[RTL] Correlation Between Process Variation and Setup/Hold Time
As an RTL engineer, when I run synthesis or do STA (Static Timing Analysis), I come across PVT…
-
-
[Verilog] Asynchronous Signal Processing: CDC and Metastability
In the last post, while designing the UART Rx module, I was looking at the asynchronous signal (Rx) coming from the outside…
-
[System Verilog] Overview – 4 interface
In Verilog, ports are connected with wires to communicate between modules. In System Verilog…
-
[System Verilog] Overview - 3 process, communication
Related article ✅[System Verilog] Overview – 1 introduction, data type…
-
[System Verilog] Overview – 2 control flow
You can control the flow of System Verilog with specific conditions or loops.
-
AMBA - 3 AXI overview
AXI (Advanced eXtensible Interface) is a bus used in high performance, high frequency systems…
![[Verilog] 비동기 신호 처리: CDC와 Metastability](data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%20727%20322'%3E%3C/svg%3E)
