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The story of a non-major becoming an RTL engineer
  • Sigmoid & Tanh
    AI & HW Fundamentals

    AI Architecture 2. The Cost of Activation: Free ReLU vs. Expensive Sigmoid

    In the previous post, we examined how expensive the MAC (Multiply-Accumulate) operation—the core of artificial neurons—is in terms of hardware, specifically regarding Multiplier area and Memory Bandwidth.

  • AI & HW Fundamentals

    AI Architecture 1. Anatomy of an Artificial Neuron: Y=WX+B on Silicon

    When starting with deep learning, the first concept we encounter is the Perceptron,

  • Glitch free clock mux waveform
    RTL engineer

    [Verilog] RTL Design: Glitch-free Clock Mux

    As low-power design becomes more important, Dynamic Frequency Scaling (DFS) technique,

  • Verilog

    [Verilog] Mastering Parameters and Generates for Reusable RTL

    When designing RTL, there are many times when you need modules that perform similar functions but differ only in bit width or pipeline depth.

  • FSM 예시
    Verilog

    [Verilog] FSM (Finite State Machine) RTL Design Principles

    All digital systems are broadly divided into two parts: the data path, which processes data,

  • Verilog

    [RTL] RTL Arithmetic: Bit Extension, Saturation Operations, and Rounding

    When designing RTL, you declare wire [7:0] a, b, c…

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