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The story of a non-major becoming an RTL engineer
  • RRAM Research

    About RRAM – 6 Filament Materials: OxRAM vs. CBRAM

    So far, we've been talking about "when voltage is applied, a filament is formed." But "that..."

  • ASIC SRAM VS FPGA SRAM
    RTL engineer

    [SRAM Part 2] Practical SRAM Verilog! Analyzing the Differences Between FPGAs and ASICs

    In the previous part, we covered the port structure and basic concepts of SRAM. This time, we will look at ‘practical…

  • RRAM 측정 회로
    RRAM Research

    About RRAM – 5 Pulse measurement and impedance matching

    There's a mystery that plagues many RRAM researchers: "When measured with DC Sweep…

  • FPGA

    [FPGA] Solving Timing Violations: False Path and Multicycle Path

    I ran the implementation in Vivado, and the WNS (Worst Negative Slack) was negative, which is the Design Timing…

  • SRAM port 설명
    RTL engineer

    [SRAM Part 1] SRAM Basic Concepts and Port Configuration (Single, Simple, True Dual)

    In digital circuit design, what is just as important as logic is the data storage…

  • Forming voltage
    RRAM Research

    About RRAM – 4 Forming and Compliance Current

    What's the most common mistake RRAM researchers make? Mishandling the process?

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