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The story of a non-major becoming an RTL engineer

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The story of a non-major becoming an RTL engineer
  • 글 설명 이미지, 반도체 8대 공정
    Semiconductor process

    Overview of the eight major semiconductor processes

    Manufacturing semiconductors requires a number of steps. There are eight major stages:

  • 글 설명 이미지, EDA playground
    Verilog

    [Verilog] Simulation Environment Settings (EDA Playground, Icarus Verilog)

    In this article, we will look at an overview of Verilog, one of the HDLs, and its simulation methods.

  • 글 설명 이미지, IP verification block diagram
    RTL engineer

    [LIN] 3 IP verification

    After months of work on the LIN controller IP RTL design,...

  • 글 설명 이미지, LIN frame
    RTL engineer

    [LIN] 2 Schedule table Description

    LIN routes all communications through a schedule table to prevent overload… .

  • 글 설명 이미지, VIO 모듈
    FPGA

    [FPGA] VIO User Guide, Pin Test

    The Need for FPGA Testing Using VIO FPGA verification involves many variables and many…

  • 글 설명 이미지, Block memory 설정
    FPGA

    [FPGA] Block memory module Setup and Usage guide

    When FPGA synthesis is performed, memory is also converted from vivado to block memory, just like clock wiz (DCM).

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