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The story of a non-major becoming an RTL engineer
  • 글 설명 이미지, Lift off 과정
    Semiconductor process

    [Photolithography] Photo Process Issues – PEB (Post-expose baking), Lift-off

    In this article, I will talk about what I experienced while working on the photo process during my master’s degree…

  • 글 설명 이미지, Aligner 구조
    Semiconductor process

    Understanding Aligner – Structure, How It Works, and Issues

    While I was working on my master's degree, I was in charge of the Aligner, an exposure equipment, and I learned about this equipment…

  • 글 설명 이미지, 인스턴스화
    Verilog

    [Verilog] Grammar 2 – Instantiation, Flip-Flops, and Latches

    Continuing from my last post, I'll explain Verilog grammar. Related articles…

  • 글 설명 이미지
    Verilog

    [Verilog] Grammar 1 – Basic Structure, Procedural Assignment, and Continuous Assignment

    In this article, we'll explore the basic syntax of Verilog. First, you need to know...

  • 글 설명 이미지, 포토 공정 순서
    Semiconductor process

    [Semiconductor Process] Photolithography

    This time, we'll take a closer look at photolithography. First, let's take a look at the overall process sequence...

  • 글 설명 이미지, 산화 공정
    Semiconductor process

    [Semiconductor Process] Oxidation

    Oxidation is a process that creates an oxide film on a wafer. Related…

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