Once RTL coding is complete and functional verification (simulation) is complete, the design transitions to the physical world (physical design). At this point, back-end engineers and foundries ask the designer these questions:
"What type of SRAM will you use? HDE, HSE, or VT?"
If you answer this question with “Just use whatever fits the capacity,” you could end up with a disaster where the chip area becomes unnecessarily large (increased cost) or the battery quickly runs out (power consumption).
In this article, we will analyze the physical types of ASIC memory, namely density type and threshold voltage type, and explore the PPA strategy for selecting the optimal memory for each situation.
1. SRAM is also selected based on its ‘purpose’.
FPGAs have no choice because they use BRAM that is already embedded in the chip, but ASICs can create thousands of combinations of memory through Memory Compilers provided by foundries (TSMC, Samsung, GF, etc.).
The basis for selection is always the trade-off between Power, Performance, and Area (PPA). It's crucial to understand the law of equivalent exchange: if you gain one, you inevitably lose another.
2. Area vs. Speed: Choosing a Bitcell Type (HDE vs. HSE)
The first decisions to be made are "how small (area)" and "how fast (speed)." These are determined by the size of the bitcell, the smallest unit for storing data.
① HDE (High Density Effect / High Density)
As the name suggests, this is high-density SRAM. It is designed to prioritize area reduction.
- Characteristic: The bitcell is the smallest in size. The transistors are placed very closely together.
- Merit: It is advantageous in reducing chip unit cost as it can minimize chip area.
- disadvantage: The transistors are small and the wiring is thin, so the current driving capability is low, which means the speed is slow.
- Recommended Uses: Large buffers, FIFOs, and simple data storage where speed is not critical. (Used by default in most SoCs.)
② HSE (High Speed Effect / High Performance)
Using for speed. Some foundries call it SP (Single Port) or HP (High Performance).
- Characteristic: Compared to HDE, the bitcell size is larger. It uses thicker wiring and larger transistors.
- Merit: Very fast operation speed (short access time)
- disadvantage: It takes up a lot of space and has a larger leakage power than HDE.
- Recommended Uses: CPU's L1/L2 cache, Critical Path with very tight timing, high-speed network packet processing.
Summary: “Start your design with HDE, and only replace it with HSE where timing errors (setup violations) are unacceptable.” This is the rule of thumb.
3. Power vs. Speed: Choosing Threshold Voltage (VT)
Once you've chosen the bitcell type, you'll need to select the transistor's threshold voltage (VT) option. This directly affects the chip's power consumption (specifically, leakage power).
① HVT (High VT) – “Heavy faucet”
- Characteristic: The threshold voltage is high, meaning a high voltage must be applied to turn the transistor on. Normally, it struggles to turn on.
- merit: When turned off, there is virtually no leakage current. This minimizes leakage power, which is essential for creating chips that last a long time.
- disadvantage: It takes a long time to turn on. The movement speed is slow.
- Usage: Always-on blocks, mobile devices, IoT sensors.
② RVT / LVT (Regular / Low VT) – “Light faucet”
- Characteristic: The threshold voltage is low. Even a slight touch causes the transistor to turn on.
- Merit: The switching speed is very fast, enabling High Performance .
- disadvantage: The faucet is loose, so water leaks out even when I turn it off. The leakage power is enormous. The chip gets hot (heating issue).
- Usage: CPU cores, high-speed calculators that operate at GHz.
4. Practical Combination Guide (Case Study)
So how do you combine these options in practice? The foundry library names (e.g., SP_HDE_HVT_...) provide a clue to the combination.
| Scenario | Recommended combination | Reason |
| Typical SoC design | HDE + RVT | A combination of both the right area and the right speed. Most commonly used. |
| Low-power IoT/mobile | HDE + HVT | The speed may be slow, but the leakage power is reduced to the extreme for the sake of the battery. |
| High-performance AI accelerator | HDE + LVT | The amount of data is large, so the area (HDE) must be saved, but the computation speed (LVT) must be fast. |
| CPU L1 Cache | HSE + LVT | Achieving maximum speed even at the expense of area and power. |
5. Conclusion: Become an engineer who reads specs.
As a junior engineer, it's easy to think, "SRAM is just a place to store data." But as you advance to senior levels, you'll need to consider, "Which SRAM should I choose to control heat generation and reduce chip area?"
The fate of the final chip depends entirely on whether the RTL code you write is synthesized into SP_HDE_HVT or SP_HSE_LVT.
Open the datasheet for the foundry library you're using right now. Compare the Leakage, Power, and Access Time numbers listed there—that's the first step toward becoming a true ASIC engineer.
References: wikichip
