ASIC - RTLearner

[SRAM Part 3] ASIC Designer's Guide to SRAM Selection: HDE vs. HSE, HVT vs. RVT

Once the RTL coding is complete and functional verification (simulation) is completed, the design is now ready for implementation in the physical world (Physical…

RTL engineer

[SRAM Part 2] Practical SRAM Verilog! Analyzing the Differences Between FPGAs and ASICs

In the previous part, we covered the port structure and basic concepts of SRAM. This time, we will look at ‘practical…

RTL engineer

[SRAM Part 1] SRAM Basic Concepts and Port Configuration (Single, Simple, True Dual)

In digital circuit design, what is just as important as logic is the data storage…

Verilog

[Verilog] Asynchronous Signal Processing: CDC and Metastability

In the last post, while designing the UART Rx module, I was looking at the asynchronous signal (Rx) coming from the outside…

[SRAM Part 3] ASIC Designer's Guide to SRAM Selection: HDE vs. HSE, HVT vs. RVT

[SRAM Part 2] Practical SRAM Verilog! Analyzing the Differences Between FPGAs and ASICs

[SRAM Part 1] SRAM Basic Concepts and Port Configuration (Single, Simple, True Dual)

[Verilog] Asynchronous Signal Processing: CDC and Metastability

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