[SRAM Part 2] Practical SRAM Verilog! Analyzing the Differences Between FPGAs and ASICs

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In the previous part, we covered the port structure and basic concepts of SRAM, and this time we will focus on the ‘real-world code (RTL)’.

Simply declaring a reg and hoping the tool will automatically create it (inference) is convenient, but it's difficult to precisely control. Therefore, experienced FPGA engineers and ASIC designers directly instantiate memory macros provided by the manufacturer.

In this article, we will compare the code that instantiates memory in FPGA (Xilinx XPM) and ASIC (Foundry Library) environments one-on-one and analyze the crucial differences hidden within them.

Related articles

✅[FPGA] Block memory module Setup and Usage guide

✅[SRAM Part 1] SRAM Basic Concepts and Port Configuration (Single, Simple, True Dual)

✅[SRAM Part 3] ASIC Designer's Guide to SRAM Selection: HDE vs. HSE, HVT vs. RVT

1. FPGA method: XPM macro instancing (Xilinx example)

The latest Xilinx FPGA designs are moving away from the IP Catalog (GUI) and toward directly calling Xilinx Parameterized Macros (XPMs) within the code. This approach is structurally very similar to using ASIC libraries.

However, you need to carefully check the configuration of the pin.

// 1. FPGA Style: XPM Instantiation
// Directly instantiate the standard macros provided by Xilinx.
module fpga_sram_wrapper (
    input  wire        clk,
    input  wire        en,      // Active High
    input  wire        we,      // Active High
    input  wire [10:0] addr,
    input  wire [31:0] wdata,
    output wire [31:0] rdata
);

    // xpm_memory_spram: Xilinx Single Port RAM Macro
    xpm_memory_spram #(
        // --- Parameters (function settings) ---
        .MEMORY_SIZE        (2048 * 32),    // Capacity (in bits)
        .MEMORY_PRIMITIVE   ("block"),      // Using BRAM
        .READ_LATENCY       (1),            // Use Output Register (1 cycle)
        .WRITE_DATA_WIDTH_A (32),
        .READ_DATA_WIDTH_A  (32),
        .ADDR_WIDTH_A       (11)
    ) u_xpm_sram (
        // --- Functional Ports (Active High Mainly) ---
        .clka  (clk),
        .rsta  (1'b0),          // Reset (not used, sometimes used)
        .ena   (en),            // Enable: Active High (Active when set to '1')
        .wea   (we),            // Write Enable: Active High
        .addra (addr),
        .dina  (wdata),
        .douta (rdata)
    );

endmodule

Characteristic: Capacity and latency are set through parameters, and the control signals (ena, wea) are designed as Active High.

2. ASIC method: Foundry library instance

On the other hand, ASIC memories generated by Memory Compiler of foundries (TSMC, Samsung, GF, etc.) have a similar shape, but the physical control pins are exposed at the front.

// 2. ASIC Style: Vendor Library Instantiation
// Connect the black box model of the foundry 28nm process.
module asic_sram_wrapper (
    input  wire        clk,
    input  wire        user_en,      // User wants Active High
    input  wire        user_we,      // User wants Active High
    input  wire [10:0] user_addr,
    input  wire [31:0] user_wdata,
    output wire [31:0] user_rdata
);

    // ASIC SRAM Instancing (Vendor Specific Name)
    // SP_HD_RVT_2048x32: Single Port, High Density, Regular VT
    SP_HD_RVT_2048x32 u_sram_macro (
        // --- Functional Pins (Caution: Active Low!) ---
        .CLK    (clk),
        .CEN    (~user_en),       // Chip Enable (Active Low) -> Invert required!
        .WEN    (~user_we),       // Global Write Enable (Active Low) -> Inversion required!
        .A      (user_addr),
        .D      (user_wdata),
        .Q      (user_rdata),

        // --- Physical / Yield Pins (Yield/Voltage Control) ---
        .EMA    (3'b010),         // Extra Margin Adjustment (Voltage Margin Adjustment)
        .EMAW   (2'b00),          // Write Assist Setting
        .RET1N  (1'b1)            // Retention Mode (1=Normal, 0=Sleep)
    );

endmodule

Although both codes use the "instance" method, their content is distinctly different. Let's analyze three key differences.

3. Key Difference ①: Parameters vs. Hardcoding

If you look at the XPM code of the FPGA, there is a parameter such as .MEMORY_SIZE.

  • FPGA: If an engineer simply changes the number in the code from 2048 to 4096, the synthesis tool will automatically internally increase the BRAM resources by 2 or 4 and attach them. It's very flexible.
  • ASIC: There are no parameters in the code. The name SP_HD_RVT_2048x32 itself is a pre-built (hardened) physical block. If you want to change the capacity, you must re-run the Memory Compiler to obtain a library with a new name.

4. Key Difference ②: Polarity Trap

가장 큰 함정은 제어 신호의 극성.

  • FPGA (ena, wea): If you look at the XPM manual, it defaults to Active High. It turns on when “Enable=1” is set. It’s intuitive.
  • ASIC (CEN, GWEN): Most commercial SRAMs use Active Low.
    • If you look at ~user_en in the code above, the CEN (Chip Enable) pin of the ASIC library operates when it is ‘0’, so you must invert the user’s ‘1’ signal to NOT (~).
    • This is the most common mistake made during ASIC porting.

5. Key Difference ③: Physical pins hidden behind abstraction (EMA, DFT)

There are pins that are present in the ASIC code but not in the FPGA code (XPM). These are pins for yield and test of the chip.

  • EMA (Extra Margin Adjustment): When performance varies across chips due to process refinement, the value of this pin is adjusted (e.g., 3'b010 -> 3'b011) to forcibly increase the internal SRAM timing margin. This is a "CPR" pin that revives dead chips.
ASIC SRAM VS FPGA SRAM

6. Conclusion

While XPM instancing in FPGAs and Standard Cell instancing in ASICs may seem similar on the surface, they present a clear difference: “flexibility (FPGA) vs. optimization (ASIC).”

When FPGA engineers begin ASIC design, it's a mistake to simply assume, "Just change the SRAM module name." They need to meticulously observe the physical specifications, including checking the CEN polarity and finding the EMA value in the datasheet.

Related articles

✅[FPGA] Block memory module Setup and Usage guide

✅[SRAM Part 1] SRAM Basic Concepts and Port Configuration (Single, Simple, True Dual)

✅[SRAM Part 3] ASIC Designer's Guide to SRAM Selection: HDE vs. HSE, HVT vs. RVT

References: AMD

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