In digital circuit design, memory, which stores data, is just as important as logic. When designing FPGAs or ASICs, you'll need to go beyond simple registers or D-FlipFlops. SRAM (Static Random Access Memory) is essential for efficiently managing large amounts of data.
However, when you actually open the IP Catalog to instantiate memory or look at the Memory Compiler specifications, it is easy to get confused by the various options such as Single Port, Simple Dual Port, and True Dual Port.
In this article, we'll clearly explain how SRAM differs from registers from an engineer's perspective, what types exist based on port configuration, and when to use them.
1. D-FlipFlop(Register) vs SRAM: Why use SRAM?
The first storage elements you learn about in digital logic circuits classes are latches and flip-flops. But why bother using complex, separate SRAM blocks within a chip? The key lies in area efficiency (density).
- D-FlipFlop (Register): Storing one bit typically requires 20 to 30 transistors, and takes up a lot of space due to clock routing and reset logic. However, it is very fast and can retrieve values immediately.
- SRAM (Static RAM): It typically uses only six transistors (6T Cells) to store one bit. It uses an interlocked latch structure, and unlike DRAM, which requires refreshing, data is retained as long as power is supplied.
If a 1MB (approximately 8 million bits) data set were implemented solely using flip-flops, it would occupy most of the chip area, resulting in inefficiency. Therefore, the basic design principle is to separate registers for small capacity and fast control, and SRAM for large data storage.
2. SRAM operating principles and port concept
SRAM consists of a "cell array" that stores data and an "interface" that communicates with the outside world. We call this interface a "port."
A port is essentially a bundle of the following signals:
- Address: Address of where data is stored
- Data In/Out: Data to write and read
- Control: Enable, Write Enable, Clock
While more ports allow for simultaneous multi-tasking, increasing bandwidth, the downside is the complexity of the wiring within the SRAM cell, resulting in a larger area. Therefore, it's crucial to select the minimal port configuration that best suits your design goals.
3. Three classifications of SRAM based on function
Let's take a closer look at the three most common types encountered in design tools (Vivado, Quartus, Memory Compiler, etc.).
① Single Port (1RW)
This is the most basic and smallest form factor. Since it has only one port, it can perform only one operation per clock cycle: either a "read" or a "write."
- Characteristic:
- There is one address bus.
- The Data In and Data Out ports may be separate or combined (Bi-directional).
- The area is the smallest (High Density).
- When do we use it?
- If concurrent access is not required.
- In cases where it is mainly read-only, such as the CPU's Instruction Memory.
- Look-up Table (LUT)
- Large buffers whose area must be minimized.
② Simple Dual Port (Pseudo Dual Port / 1R1W)
Although the word "simple" makes it seem like it has few features, it's actually a crucial structure at the heart of First-In First-Out (FIFO) design. In FPGAs, it's often called a Pseudo Dual Port.
- Structure: It has two ports (Port A, Port B).
- Port A: Write Only
- Port B: Read Only
- Characteristic:
- Simultaneous reading and writing to different addresses is possible.
- It has a larger area than a Single Port, but smaller than a True Dual Port.
- When do we use it?
- FIFO: It is optimized for a structure that continuously accumulates data on one side (Write) and continuously takes it out on the other side (Read).
- Data logging system.
③ True Dual Port (2RW)
This is the most flexible, but also the most expensive (in terms of area and power) architecture. The two ports operate completely independently.
- Structure: Port A and Port B are perfectly symmetrical.
- Port A: Readable / Writeable
- Port B: Readable / Writeable
- Characteristic:
- Two ports can simultaneously Write/Write, Read/Read, and Read/Write to different addresses.
- Collision: If two ports attempt to write to the same address simultaneously, or if one port attempts to write and the other attempts to read, data may be corrupted or rendered unknown. Collision avoidance logic may be required to prevent this.
- When do we use it?
- Shared Memory: When two different masters (e.g., a CPU and a hardware accelerator) share a single memory and exchange data.
- Complex cache structures or scratchpad memory.
4. Summary and Comparison
| Division | Port | Concurrent | Application | Area (relative) |
| Single Port | 1 (RW shared) | No (R or W) | LUT, simple buffer | Small |
| Simple Dual Port | 2 (1 Write, 1 Read) | Possible (Write & Read) | FIFO, buffering | Medium |
| True Dual Port | 2 (2 RW) | Possible (Any Mix) | Multiprocessor shared memory | Large |
5. Conclusion
When selecting SRAM, choosing a True Dual Port with a multitude of features isn't always the answer. True Dual Ports can take up nearly twice the area of single-port memory and consume significantly more power. Therefore, accurately understanding the data flow of the module you're designing and selecting the necessary port configuration is the first step toward optimization.
References: AMD
