[Verilog] FSM (Finite State Machine) RTL Design Principles
All digital systems are broadly divided into two parts: the data path, which processes data,
-
-
[RTL] RTL Arithmetic: Bit Extension, Saturation Operations, and Rounding
When designing RTL, you declare wire [7:0] a, b, c…
-
[RTL] SDC, Introduction to Timing Constraints
“My code is perfect, so why doesn’t the chip work?”
-
[RTL] RTL Valid-Ready Handshake and Skid Buffer
When designing RTL, there inevitably comes a point where you find yourself in a dilemma: "Timing..."
-
[SRAM Part 3] ASIC Designer's Guide to SRAM Selection: HDE vs. HSE, HVT vs. RVT
Once the RTL coding is complete and functional verification (simulation) is completed, the design is now ready for implementation in the physical world (Physical…
-
[SRAM Part 2] Practical SRAM Verilog! Analyzing the Differences Between FPGAs and ASICs
In the previous part, we covered the port structure and basic concepts of SRAM. This time, we will look at ‘practical…
