About RRAM - 3 Crossbar array and Sneak Path Current

It's been a really long time since I wrote about RRAM, so I thought I'd summarize it before it completely fades from my memory.

In the previous two parts, we explored the operating principles (filament theory) and characteristics of a single RRAM device. However, in the semiconductor business, a single device has no value. Billions of devices must be integrated to create a "memory chip."

The primary reason RRAM is attracting attention as a next-generation memory is its Crossbar Array architecture, which theoretically allows for the smallest possible area. However, this architecture suffers from a critical drawback: Sneak Path Current (leakage current).

In this article, we will explain the Crossbar Array structure that determines the integration density of RRAM, the Sneak Path Current that interferes with it, and the Selector technology that is the solution.

1. What is a Crossbar Array structure?

Conventional memory (DRAM, NAND) has limited integration due to its complex transistor and capacitor structures. In contrast, RRAM's Crossbar Array structure is remarkably simple.

Structural features

• Word Line and Bit Line: The wiring crosses in a grid pattern.
• Crosspoint: The RRAM element (Metal-Insulator-Metal) is sandwiched between the wires.
• Merit:
  1. Cell Size: The area is determined solely by the wiring width (F) without transistors, so theoretically the highest density is possible.
  2. Stackable: It is advantageous to continue stacking upwards like 3D NAND (3D Crosspoint Memory).

2. Fatal Problem: Sneak Path Current

The crossbar structure is a double-edged sword because all wires are connected. When attempting to read a specific cell, current leaks through unwanted sneak paths.

Occurrence mechanism

Let's say we want to read the red cell (HRS).

1. Intention: Apply voltage to the selected Word Line and measure the current flowing to the Bit Line. Since the HRS cell has high resistance, there should be almost no current flowing.
2. Reality (Sneak Path): But what if there are LRS cells around that cell (blue) Instead of passing through the HRS cell with high resistance, the current flows through the surrounding cells with low resistance.
3. Result (Read Failure): The sense amplifier judges, “Huh? There’s a lot of current flowing?” and misjudges the target cell as LRSinstead of HRS.

Due to this problem, a passive crossbar arraywith only a single element (resistor) cannot be scaled up to large capacity.

3. Solution 1: 1T1R (1 Transistor – 1 Resistor)

The most obvious solution is to add a transistor to each RRAM element.

• Principle: Since current flows only when the gate of the transistor is opened, the sneak path can be completely blocked.
• disadvantage: The inclusion of transistors increases the area, making it unsuitable for high-density memory (Storage Class Memory) and primarily used as a replacement for Embedded Flash. 대체용으로 쓰입니다.

4. Solution 2: 1S1R (1 Selector – 1 Resistor)

For high-density memory, instead of transistors, a selector with only two terminals, which acts as a switch, is required. The structure that stacks this in series with RRAM is called 1S1R..

The Role of Selectors (Nonlinearity)

A selector is similar to a diode.

• Low Voltage (Sneak Path Section): Turns off the current. Prevents microcurrents from leaking in from the surroundings.
• High voltage (Read/Write section): Passes current (ON).

That is, by taking advantage of the characteristic that the door opens only when a certain voltage (Threshold Voltage, V_th) is exceeded, it allows only selected cells to be accurately read and written.

Types of Selectors

1. Ovonic Threshold Switch (OTS): A core technology used in Intel's 3D XPoint. It utilizes the phase transition of chalcogenide materials and boasts extremely fast switching speeds.
2. Mott Insulator (MIT): It uses a material whose properties change from insulator metal depending on the voltage.
3. Mixed Ionic-Electronic Conduction (MIEC): This is a method that utilizes the movement of ions and electrons simultaneously.

5. Conclusion and Summary

For RRAM to be used as next-generation memory, establishing a reliable 1S1R structureis essential.

• Crossbar Array: Although the integration is high, interference occurs because all paths are connected.
• Sneak Path: A fatal error in which current leaks into surrounding low-resistance (LRS) cells, causing data to be misread.
• Selector (1S1R): A key component that suppresses sneak paths by blocking current at low voltages and allowing it to flow only at high voltages.

References: Memristive devices for computing