ILA(Integrated Logic Analyzer) Explanation
When conducting FPGA testing, there are times when you need to verify signals. While signals coming from IO pins can be verified with an oscilloscope, internal signals cannot. ILA is a monitoring module built into Vivado during bit file synthesis, and is used to monitor desired signals. Let's learn how to use it.
Creation Method
First, select IP Catalog in the Project Manager on the far left of the Xilinx Vivado window.
When you select IP Catalog, the following window appears; search for ILA and select it.
Then the following window appears, and I will explain the parts you need to input one by one.
Component name
First, you need to check the Component Name. There's a default, but you can change it. You'll want to make sure you enter this name correctly when instantiating it in RTL to avoid errors, right?
Number of probes, Sample Data Depth
Next, you need to modify the Number of probesand Sample Data Depth. The Number of Probes indicates the number of signals you want to monitor. The Sample Data Depth indicates the size of the memory being monitored. Increasing the Depth allows you to observe how signals change over time, but it consumes resources, extending synthesis time and potentially causing tests to not run properly.
After modifying the settings, the diagramwill automatically change as shown below.
2nd page
In the second window, you can change the width of each signal. Signals like address are usually 32 bits, so of course you'll need to change them, right? I set the option to monitor two signals.
After setting this up and pressing OK, the following window will appear. If you press Generate, it will be automatically generated and you can then check the creation in IP sources.
Instantiation
Now that it's created, you can instantiate it in RTL by writing the following code:
ila_0 u_ila0 (
.clk (clk0 )
,.probe0 (wire_0)
,.probe1 (wire_1)
);Here, wire_0 and wire_1 are the signals I want to monitor, and clk0 is the sampling clock. Naturally, I need to assign them to the internal clock, right? However, one thing to note is that you need to connect a clock that starts as soon as the board powers up. I'll explain what this means in the final note.
How to use
Bit File Download
When you synthesize the bit file with ILA included in the RTL design, an ltx file is generated. When loading the bit file onto the board, you must also include this ltx file to enable monitoring.
Actual Usage Example
After installing the bit file on the board, the following window will appear in vivado.
the red boxshows the signals I wanted to monitor. I want to monitor 1-bit wire_0 and 32-bit wire_1.
Now, we need to configure the signal monitoring options. First, let's look at the blue box 부분을 살펴보겠습니다.
Remember how I explained that Sample Data Depth refers to the size of the monitored memory? Trigger position in windowdetermines which part of the user-defined depth will trigger. For example, if the depth is 8192 and the trigger position is 4096, you'll be able to see halfway around the user-defined trigger point. However, this isn't always necessary, so I usually set it to a small value (like 100 or 1000).
Next, you need to modify the the yellow box. 부분의 옵션을 수정해 봅시다.
Here, you set the trigger conditions. You need to select the trigger signal and set the trigger condition. (High level, Low level, Rising edge, Falling edge, etc.)
Now that you've completed all the settings, simply click Run to begin monitoring. This will change the status from IDLE to Waiting for Trigger, and once you start testing, you'll see a signal at the trigger point you specified.
Then it will change from IDLE to Waiting for Trigger and when you start the test you will be able to see the signal of the trigger point you set.
Precautions for Use
Clock Type
There are some caveats to using the ILA module. First, the sampling clock fed into the module must be a clock that starts as soon as the board is powered on. Depending on the user's design, there may be multiple clock sources in the synthesized project, but you must use a clock that comes in as soon as the power is turned on, such as EXT_clock. Otherwise, the following warning message appears, and monitoring may become impossible.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7k410t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).Clock Frequency
The next thing to note is that you cannot monitor signals that have a frequency faster than the sampling clock frequency. In my experience, monitoring didn't work even if the frequency was similar to the ILA clock...
Therefore, it is recommended to use the fastest clock possible for the ILA sampling clock. Of course, the first condition above must also be met!!
References: ILA Data sheet
