{"id":732,"date":"2024-09-30T08:41:12","date_gmt":"2024-09-29T23:41:12","guid":{"rendered":"https:\/\/rtlearner.com\/?p=732"},"modified":"2025-12-04T13:42:43","modified_gmt":"2025-12-04T04:42:43","slug":"verilog-uart-rtl-design-3","status":"publish","type":"post","link":"https:\/\/rtlearner.com\/en\/verilog-uart-rtl-design-3\/","title":{"rendered":"[Verilog] UART RTL design 3"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">\uc774 \uae00\ub85c UART RTL design\uc744 \ub9c8\ubb34\ub9ac\ud558\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-table-of-content-nav.kb-table-of-content-id732_cd551d-bf .kb-table-of-content-wrap{padding-top:var(--global-kb-spacing-sm, 1.5rem);padding-right:var(--global-kb-spacing-sm, 1.5rem);padding-bottom:var(--global-kb-spacing-sm, 1.5rem);padding-left:var(--global-kb-spacing-sm, 1.5rem);box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kb-table-of-content-nav.kb-table-of-content-id732_cd551d-bf .kb-table-of-contents-title-wrap{padding-top:0px;padding-right:0px;padding-bottom:0px;padding-left:0px;}.kb-table-of-content-nav.kb-table-of-content-id732_cd551d-bf .kb-table-of-contents-title{font-weight:regular;font-style:normal;}.kb-table-of-content-nav.kb-table-of-content-id732_cd551d-bf .kb-table-of-content-wrap .kb-table-of-content-list{font-weight:regular;font-style:normal;margin-top:var(--global-kb-spacing-sm, 1.5rem);margin-right:0px;margin-bottom:0px;margin-left:0px;}@media all and (max-width: 767px){.kb-table-of-content-nav.kb-table-of-content-id732_cd551d-bf .kb-table-of-contents-title{font-size:var(--global-kb-font-size-md, 1.25rem);}.kb-table-of-content-nav.kb-table-of-content-id732_cd551d-bf .kb-table-of-content-wrap .kb-table-of-content-list{font-size:var(--global-kb-font-size-sm, 0.9rem);}}<\/style>\n\n<style>.kadence-column732_38ccc5-13 > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column732_38ccc5-13 > .kt-inside-inner-col,.kadence-column732_38ccc5-13 > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column732_38ccc5-13 > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column732_38ccc5-13 > .kt-inside-inner-col{flex-direction:column;}.kadence-column732_38ccc5-13 > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column732_38ccc5-13 > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column732_38ccc5-13{position:relative;}@media all and (max-width: 1024px){.kadence-column732_38ccc5-13 > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column732_38ccc5-13 > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column732_38ccc5-13\"><div class=\"kt-inside-inner-col\">\n<p class=\"wp-block-paragraph\"><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705<a href=\"https:\/\/rtlearner.com\/verilog-simulation-settings\/\">[Verilog] Simulation \ud658\uacbd \uc138\ud305 (EDA playground, Icarus verilog)<\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-1\/\">[Verilog] UART RTL design 1<\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-2\/\">[Verilog] UART RTL design 2<\/a><\/p>\n<\/div><\/div>\n\n\n\n<h2 class=\"wp-block-heading\">UART RTL design<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Rx controller RTL design<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Tx controller\ub97c \uc774\ud574\ud558\uc168\ub2e4\uba74 Rx controller\ub294 \uc774\ud574\ud558\uae30 \uc26c\uc6b0\uc2e4 \uac81\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><pre class=\"code-block-pro-copy-button-pre\" aria-hidden=\"true\"><textarea class=\"code-block-pro-copy-button-textarea\" tabindex=\"-1\" aria-hidden=\"true\" readonly>module uart_rx_ctrl (\n     input  wire        pclk\n    ,input  wire        presetn\n\n    ,input  wire        uclk_en\n\n    ,input  wire        uart_in\n    ,input  wire        complete_clr\n    ,input  wire        parity_en\n    ,input  wire        stop_en\n\n    ,output wire &#91; 7:0&#93; uart_data\n    ,output wire        complete\n    ,output wire        uart_rx\n);\n\n    \/\/===================================================================\n    \/\/ Local Parameters\n    \/\/===================================================================\n    localparam IDLE        = 3'h0,\n               START       = 3'h1,\n               DATA        = 3'h2,\n               PARITY      = 3'h3,\n               STOP        = 3'h4,\n               TRANSFINISH = 3'h5;\n\n    reg  &#91; 2:0&#93; r_cur_st;\n    reg  &#91; 2:0&#93; r_nxt_st;\n    reg  &#91; 7:0&#93; r_bitcnt;\n\n    reg         r_complete;\n    reg  &#91; 7:0&#93; r_shift;\n\n    wire        data_end;\n    wire        uart_init;\n\n    \/\/rx_init\n    reg r_uart_in;\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)          r_uart_in &lt;= 1'h1;\n        else                   r_uart_in &lt;= uart_in;\n    end\n\n    \/\/cur_st\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)          r_cur_st &lt;= IDLE;\n        else if (complete_clr) r_cur_st &lt;= IDLE;\n        else                   r_cur_st &lt;= r_nxt_st;\n    end\n\n    \/\/FSM\n    always @(*) begin\n        case (r_cur_st)\n            IDLE        : begin\n                if (uart_init) begin\n                     r_nxt_st &lt;= START;\n                end\n                else r_nxt_st &lt;= IDLE;\n            end\n            START       : begin\n                if (uclk_en) begin\n                     r_nxt_st &lt;= DATA;\n                end\n                else r_nxt_st &lt;= START;\n            end\n            DATA        : begin\n                if (data_end &amp; parity_en) begin\n                     r_nxt_st &lt;= PARITY;\n                end\n                else if (data_end &amp; !parity_en &amp; stop_en) begin\n                     r_nxt_st &lt;= STOP;\n                end\n                else if (data_end &amp; !parity_en &amp; !stop_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= DATA;\n            end\n            PARITY      : begin\n                if (stop_en &amp; uclk_en) begin\n                     r_nxt_st &lt;= STOP;\n                end\n                else if (uclk_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= PARITY;\n            end\n            STOP        : begin\n                if (uclk_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= STOP;\n            end\n            TRANSFINISH : begin\n                if (complete_clr) begin\n                     r_nxt_st &lt;= IDLE;\n                end\n                else r_nxt_st &lt;= TRANSFINISH;\n            end\n            default     : begin\n                r_nxt_st &lt;= IDLE;\n            end\n        endcase\n    end\n\n    \/\/BITCNT\n    wire data_st;\n    assign data_st = (r_cur_st == DATA);\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_bitcnt &lt;= 8'h0;\n        else if (complete_clr)      r_bitcnt &lt;= 8'h0;\n        else if (data_st &amp; uclk_en) r_bitcnt &lt;= (r_bitcnt + 1);\n        else                        r_bitcnt &lt;= r_bitcnt;\n    end\n\n    \/\/UART rx\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_shift &lt;= 8'h0;\n        else if (data_st) begin\n            if (uclk_en)            r_shift &lt;= {uart_in,r_shift&#91;7:1&#93;};\n            else                    r_shift &lt;= r_shift;\n        end\n        else                        r_shift &lt;= r_shift;\n    end\n\n    \/\/complete intr\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_complete &lt;= 1'b0;\n        else if (complete_clr)      r_complete &lt;= 1'b0;\n        else if ((r_cur_st == TRANSFINISH) &amp; uclk_en) begin\n                                    r_complete &lt;= 1'b1;\n        end\n        else                        r_complete &lt;= r_complete;\n    end\n\n    assign data_end  = (r_bitcnt == 8'h8);\n    assign complete  = r_complete;\n    assign uart_data = r_shift;\n    assign uart_init = ~uart_in &amp; r_uart_in;\n    assign uart_rx   = (r_cur_st != IDLE);\n\nendmodule<\/textarea><\/pre><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart_rx_ctrl (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pclk<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        presetn<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uclk_en<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_in<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        complete_clr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        parity_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        stop_en<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; uart_data<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        complete<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_rx<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Local Parameters<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">localparam<\/span><span style=\"color: #D8DEE9FF\"> IDLE        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h0<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               START       <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h1<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               DATA        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h2<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               PARITY      <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h3<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               STOP        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h4<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               TRANSFINISH <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h5<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91; <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_cur_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91; <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_nxt_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91; <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_bitcnt;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91; <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_shift;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        data_end;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_init;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/rx_init<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\"> r_uart_in;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)          r_uart_in <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;h1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                   r_uart_in <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> uart_in;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/cur_st<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)          r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr) r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                   r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/FSM<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\">) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            IDLE        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uart_init) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> START;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            START       : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> START;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            DATA        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> parity_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> PARITY;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">parity_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> stop_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">parity_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">stop_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            PARITY      : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (stop_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> PARITY;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            STOP        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            TRANSFINISH : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\">     : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/BITCNT<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> data_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> data_st <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> DATA);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr)      r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_st <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> (r_bitcnt <\/span><span style=\"color: #81A1C1\">+<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_bitcnt;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/UART rx<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_st) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en)            r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> {uart_in,r_shift&#91;<\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">&#93;};<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                    r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_shift;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_shift;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/complete intr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr)      r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> ((r_cur_st <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH) <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                                    r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> data_end  <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (r_bitcnt <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h8<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> complete  <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> uart_data <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_shift;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> uart_init <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">~<\/span><span style=\"color: #D8DEE9FF\">uart_in <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> r_uart_in;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> uart_rx   <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st <\/span><span style=\"color: #81A1C1\">!=<\/span><span style=\"color: #D8DEE9FF\"> IDLE);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #81A1C1\">endmodule<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">Rx controller\ub294 Tx controller\uc640 \ub2e4\ub974\uac8c APB register setting\uc73c\ub85c \ud1b5\uc2e0\uc744 \uc2dc\uc791\ud558\ub294 \uac83\uc774 \uc544\ub2c8\ub77c, \uc678\ubd80 controller\ub85c\ubd80\ud130 \ub4e4\uc5b4\uc628 signal\uc758 posedge signal(uart_init)\ub85c FSM\uc774 \ub3d9\uc791\ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\uc774 module\uc740 \ud55c \uac00\uc9c0 \uc218\uc815\uc774 \ud544\uc694\ud55c\ub370\uc694, \uba3c\uc800 parity check \uae30\ub2a5\uc774 \uad6c\ud604\ub418\uc5b4 \uc788\uc9c0 \uc54a\uc2b5\ub2c8\ub2e4. DATA state\uc77c \ub54c input \ub41c signal\ub85c parity\ub97c \uacc4\uc0b0\ud558\uace0 \ub9cc\uc57d PARITY state\uc5d0 input \ub41c parity\uc640 \uc77c\uce58\ud558\uc9c0 \uc54a\ub294\ub2e4\uba74 error intr\ub97c \ub0b4\ubcf4\ub0b4\uc57c \ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ub9c8\uc9c0\ub9c9\uc73c\ub85c output\uc73c\ub85c uart_rx\uac00 \uc788\ub294\ub370\uc694, Rx controller\uac00 \ub3d9\uc791\ud558\uace0 \uc788\uc74c\uc744 \ub098\ud0c0\ub0b4\ub294 signal\uc785\ub2c8\ub2e4. \uc774 signal\uc740 \uc5b4\ub514\uc5d0 \uc0ac\uc6a9\ub420\uae4c\uc694?<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Rx CLK gen RTL design<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Rx \uc6a9 CLK gen\uc5d0\ub294 \ud55c \uac00\uc9c0 \ud2b9\uc9d5\uc774 \uc788\uc2b5\ub2c8\ub2e4. \uc6b0\uc120 RTL code\ub97c \uc0b4\ud3b4\ubcfc\uae4c\uc694?<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><pre class=\"code-block-pro-copy-button-pre\" aria-hidden=\"true\"><textarea class=\"code-block-pro-copy-button-textarea\" tabindex=\"-1\" aria-hidden=\"true\" readonly>module uart_rx_clkgen (\n     input  wire        presetn\n    ,input  wire        pclk\n\n    ,input  wire        uart_rx \/\/From Rx controller\n    ,input  wire &#91; 8:0&#93; bit_div\n    ,input  wire &#91; 2:0&#93; pre_scale\n    ,input  wire &#91; 4:0&#93; bit_mult\n\n    ,output wire        rx_uclk\n);\n\n    reg         r_uclk;\n    reg  &#91; 8:0&#93; r_prescale;\n    reg  &#91;13:0&#93; r_divisor_1;\n    reg  &#91;22:0&#93; r_divisor_2;\n    reg  &#91;21:0&#93; r_dividercnt;\n\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn)    r_prescale  &lt;= 9'd0;\n        else begin\n            case (pre_scale)\n                3'd0   : r_prescale &lt;= 9'd2  ;\n                3'd1   : r_prescale &lt;= 9'd4  ;\n                3'd2   : r_prescale &lt;= 9'd8  ;\n                3'd3   : r_prescale &lt;= 9'd16 ;\n                3'd4   : r_prescale &lt;= 9'd32 ;\n                3'd5   : r_prescale &lt;= 9'd64 ;\n                3'd6   : r_prescale &lt;= 9'd128;\n                3'd7   : r_prescale &lt;= 9'd256;\n                default: r_prescale &lt;= r_prescale;\n            endcase\n        end\n    end\n\n    \/\/r_divisor_1  =  { 2^(pre_scale+1) x (bit_mult + 1) } ]\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn) r_divisor_1 &lt;= 14'd0; \n        else          r_divisor_1 &lt;= r_prescale * (bit_mult + 'b1);\n    end\n\n    \/\/r_divisor_2  =  &#91; (bit_div) x  { 2^(pre_scale+1) x (bit_mult + 1) } &#93;\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn) r_divisor_2 &lt;= 23'd0; \n        else          r_divisor_2 &lt;= r_divisor_1 * bit_div;\n    end\n\n    \/\/half cycle of serial clock = r_divisor_2 \/ 2\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn)                          r_dividercnt &lt;= 22'd0; \n        else if (uart_rx &amp; (r_dividercnt !=  r_divisor_2)) \n\t\t                               r_dividercnt &lt;= (r_dividercnt + 'b1);\n        else                                   r_dividercnt &lt;= 22'd0; \n    end\n\n    wire &#91;22:0&#93; r_divisor_2_half;\n    assign      r_divisor_2_half = r_divisor_2 >> 1;\n\n    \/\/serial clock generation\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn)                             r_uclk &lt;= 'b0;\n        else if (r_dividercnt &lt; r_divisor_2_half) r_uclk &lt;= 'b0;\n        else                                      r_uclk &lt;= 'b1;\n    end\n\n    assign rx_uclk = r_uclk;\n\nendmodule<\/textarea><\/pre><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart_rx_clkgen (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        presetn<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pclk<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_rx <\/span><span style=\"color: #616E88\">\/\/From Rx controller<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">8<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; bit_div<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; pre_scale<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">4<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; bit_mult<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_uclk<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91; <\/span><span style=\"color: #B48EAD\">8<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_prescale;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91;<\/span><span style=\"color: #B48EAD\">13<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_divisor_1;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91;<\/span><span style=\"color: #B48EAD\">22<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_divisor_2;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  &#91;<\/span><span style=\"color: #B48EAD\">21<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_dividercnt;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)    r_prescale  <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (pre_scale)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d0<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d2<\/span><span style=\"color: #D8DEE9FF\">  ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d1<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d4<\/span><span style=\"color: #D8DEE9FF\">  ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d2<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d8<\/span><span style=\"color: #D8DEE9FF\">  ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d3<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d16<\/span><span style=\"color: #D8DEE9FF\"> ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d4<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d32<\/span><span style=\"color: #D8DEE9FF\"> ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d5<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d64<\/span><span style=\"color: #D8DEE9FF\"> ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d6<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d128<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d7<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d256<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\">: r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_prescale;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/r_divisor_1  =  { 2^(pre_scale+1) x (bit_mult + 1) } ]<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) r_divisor_1 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">14&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">          r_divisor_1 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_prescale <\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\"> (bit_mult <\/span><span style=\"color: #81A1C1\">+<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/r_divisor_2  =  &#91; (bit_div) x  { 2^(pre_scale+1) x (bit_mult + 1) } &#93;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) r_divisor_2 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">23&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">          r_divisor_2 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_divisor_1 <\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\"> bit_div;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/half cycle of serial clock = r_divisor_2 \/ 2<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)                          r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">22&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uart_rx <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> (r_dividercnt <\/span><span style=\"color: #81A1C1\">!=<\/span><span style=\"color: #D8DEE9FF\">  r_divisor_2)) <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">\t\t                               r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> (r_dividercnt <\/span><span style=\"color: #81A1C1\">+<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                                   r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">22&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91;<\/span><span style=\"color: #B48EAD\">22<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; r_divisor_2_half;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\">      r_divisor_2_half <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_divisor_2 <\/span><span style=\"color: #81A1C1\">&gt;&gt;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/serial clock generation<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)                             r_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;<\/span><span style=\"color: #D8DEE9FF\"> r_divisor_2_half) r_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                                      r_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> rx_uclk <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_uclk;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #81A1C1\">endmodule<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">\uc774 module\uc740 uart_rx\uac00 high\uc77c \ub54c(Rx controller\uac00 \uc791\ub3d9\ud560 \ub54c)\ub9cc uclk\ub97c \uc0dd\uc131\ud569\ub2c8\ub2e4. \uc65c \uadf8\ub7f4\uae4c\uc694?<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Rx controller\ub294 \uc678\ubd80\uc758 controller\uc5d0\uc11c data\ub97c \ubc1b\uc2b5\ub2c8\ub2e4, \uadf8\ub807\uae30 \ub54c\ubb38\uc5d0 \uc678\ubd80 controller\uc640 baud rate\uac00 \uc644\uc804\ud788 \uc77c\uce58\ud558\uc9c0 \uc54a\uc744 \uc218 \uc788\uc2b5\ub2c8\ub2e4. \uc774\ub7f4 \uacbd\uc6b0, \ud1b5\uc2e0\uc744 \uacc4\uc18d \uc9c4\ud589\ud558\uba74 \uc2dc\uac04\uc774 \uc9c0\ub0a0\uc218\ub85d \ub450 controller\uc758 baud rate\ub294 \uc810\uc810 \ucc28\uc774\uac00 \ub0a9\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-image732_f38a8e-c4.kb-image-is-ratio-size, .kb-image732_f38a8e-c4 .kb-image-is-ratio-size{max-width:650px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image732_f38a8e-c4.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image732_f38a8e-c4 .kb-image-is-ratio-size{align-self:unset;}.kb-image732_f38a8e-c4 figure{max-width:650px;}.kb-image732_f38a8e-c4 .image-is-svg, .kb-image732_f38a8e-c4 .image-is-svg img{width:100%;}.kb-image732_f38a8e-c4 .kb-image-has-overlay:after{opacity:0.3;}.kb-image732_f38a8e-c4 img.kb-img, .kb-image732_f38a8e-c4 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image732_f38a8e-c4.kb-image-is-ratio-size, .kb-image732_f38a8e-c4 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image732_f38a8e-c4 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image732_f38a8e-c4\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/4qerd\/btsJkYclxj9\/i0kHYWJovu9A7r4HzIoMz0\/img.png\" alt=\"Simulation result\" class=\"kb-img\"\/><figcaption>Simulation result<\/figcaption><\/figure><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">\uc774\ub807\uae30 \ub54c\ubb38\uc5d0 baud rate\uc758 \ucc28\uc774\ub97c \ub9e4\ubc88 \ucd08\uae30\ud654\uc2dc\ucf1c \uc8fc\uae30 \uc704\ud574 Rx controller\uac00 \uc791\ub3d9\ud560 \ub54c\ub9cc uclk\ub97c \uc0dd\uc131\ud558\uace0, 1-byte \ud1b5\uc2e0\uc774 \ub05d\ub098\uba74 CLK gen \ub0b4\ubd80 counter\uac00 reset \ubc29\uc2dd\uc73c\ub85c \uc124\uacc4\ud588\uc2b5\ub2c8\ub2e4. \uc774\ud574\uac00 \ub418\uc168\uc73c\uba74 \uc88b\uaca0\ub124\uc694;;;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\ucc38\uace0\ub85c, UART Rx\ub294 \uc678\ubd80\uc5d0\uc11c \ube44\ub3d9\uae30 \uc2e0\ud638(Asynchronous)\ub97c \ubc1b\uac8c \ub429\ub2c8\ub2e4. \uc774\ub7f0 \uacbd\uc6b0 \uc2e0\ud638 \ucc98\ub9ac\uc5d0 \uc8fc\uc758\uac00 \ud544\uc694\ud55c\ub370\uc694, <a href=\"https:\/\/rtlearner.com\/verilog-cdc-metastability\/\">\ub2e4\uc74c \uae00<\/a>\uc5d0\uc11c \uc880 \ub354 \uc790\uc138\ud788 \uc124\uba85\ud558\ub3c4\ub85d \ud558\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Top integration<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">\uc774\uc81c \uc124\uacc4\ud55c \ubaa8\ub4c8\uc744 integration \ud558\uc5ec IP\ub97c \uc644\uc131\ud574 \ubd05\uc2dc\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><pre class=\"code-block-pro-copy-button-pre\" aria-hidden=\"true\"><textarea class=\"code-block-pro-copy-button-textarea\" tabindex=\"-1\" aria-hidden=\"true\" readonly>module uart (\n     input  wire        presetn\n    ,input  wire        pclk\n    ,input  wire        pwrite\n    ,input  wire        psel\n    ,input  wire        penable\n    ,input  wire &#91; 5:2&#93; paddr\n    ,input  wire &#91;31:0&#93; pwdata\n\n    ,output wire &#91;31:0&#93; prdata\n    ,output wire        intr\n\n    ,output wire        uart_out\n    ,input  wire        uart_in\n);\n\n    wire        tx_uclk;\n    wire        tx_uclk_en;\n    wire        rx_uclk;\n    wire        rx_uclk_en;\n\n    \/\/Register signals\n    wire &#91; 8:0&#93; bit_div;\n    wire &#91; 2:0&#93; pre_scale;\n    wire &#91; 4:0&#93; bit_mult;\n\n    wire        uart_rx;\n    wire        tx_complete;\n    wire        rx_complete;\n    wire        tx_clr;\n    wire        rx_clr;\n    wire        parity_en;\n    wire        stop_en;\n    wire        uart_en;\n    wire &#91; 7:0&#93; uart_txdata;\n    wire &#91; 7:0&#93; uart_rxdata;\n\n    reg         r_uart_in;\n    always @(negedge presetn or posedge pclk ) begin\n        if (!presetn) begin \n            r_uart_in &lt;= 1'b1;\n        end\n        else begin\n            r_uart_in &lt;= uart_in;\n        end\n    end\n\n    reg         r_tx_uclk;\n    always @(negedge presetn or posedge pclk ) begin\n        if (!presetn) begin \n            r_tx_uclk &lt;= 1'b0;\n        end\n        else begin\n            r_tx_uclk &lt;= tx_uclk;\n        end\n    end\n\n    reg         r_rx_uclk;\n    always @(negedge presetn or posedge pclk ) begin\n        if (!presetn) begin \n            r_rx_uclk &lt;= 1'b0;\n        end\n        else begin\n            r_rx_uclk &lt;= rx_uclk;\n        end\n    end\n\n    uart_apb u_apb (\n         .pclk         (pclk        )\n        ,.presetn      (presetn     )\n        ,.penable      (penable     )\n        ,.psel         (psel        )\n        ,.paddr        (paddr&#91;5:2&#93;  )\n        ,.pwrite       (pwrite      )\n        ,.pwdata       (pwdata      )\n        ,.prdata       (prdata      )\n\n        ,.bit_div      (bit_div     )\n        ,.pre_scale    (pre_scale   )\n        ,.bit_mult     (bit_mult    )\n\n        ,.tx_complete  (tx_complete )\n        ,.rx_complete  (rx_complete )\n        ,.tx_clr       (tx_clr      )\n        ,.rx_clr       (rx_clr      )\n\n        ,.uart_en      (uart_en     )\n        ,.parity_en    (parity_en   )\n        ,.stop_en      (stop_en     )\n        ,.uart_txdata  (uart_txdata )\n        ,.uart_rxdata  (uart_rxdata )\n    );\n\n    uart_tx_clkgen u_tx_clkgen (\n         .pclk         (pclk        )\n        ,.presetn      (presetn     )\n\n        ,.bit_div      (bit_div     )\n        ,.pre_scale    (pre_scale   )\n        ,.bit_mult     (bit_mult    )\n\n        ,.tx_uclk      (tx_uclk     )\n    );\n\n    uart_tx_ctrl u_tx_ctrl (\n         .pclk         (pclk        )\n        ,.presetn      (presetn     )\n        ,.uclk_en      (tx_uclk_en  )\n\n        ,.parity_en    (parity_en   )\n        ,.stop_en      (stop_en     )\n        ,.uart_en      (uart_en     )\n        ,.uart_data    (uart_txdata )\n        ,.complete_clr (tx_clr      )\n\n        ,.complete     (tx_complete )\n        ,.uart_out     (uart_out    )\n    );\n\n    uart_rx_clkgen u_rx_clkgen (\n         .pclk         (pclk        )\n        ,.presetn      (presetn     )\n\n        ,.uart_rx      (uart_rx     )\n        ,.bit_div      (bit_div     )\n        ,.pre_scale    (pre_scale   )\n        ,.bit_mult     (bit_mult    )\n\n        ,.rx_uclk      (rx_uclk     )\n    );\n\n    uart_rx_ctrl u_rx_ctrl (\n         .pclk         (pclk        )\n        ,.presetn      (presetn     )\n        ,.uclk_en      (rx_uclk_en  )\n\n        ,.uart_in      (r_uart_in   )\n        ,.complete_clr (rx_clr      )\n        ,.parity_en    (parity_en   )\n        ,.stop_en      (stop_en     )\n\n        ,.uart_data    (uart_rxdata )\n        ,.complete     (rx_complete )\n        ,.uart_rx      (uart_rx     )\n    );\n\n    assign tx_uclk_en =  tx_uclk &amp; ~r_tx_uclk;\n    assign rx_uclk_en = ~rx_uclk &amp;  r_rx_uclk;\n    assign intr       = (tx_complete | rx_complete);\n\nendmodule<\/textarea><\/pre><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        presetn<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pclk<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pwrite<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        psel<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        penable<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">&#93; paddr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91;<\/span><span style=\"color: #B48EAD\">31<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; pwdata<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91;<\/span><span style=\"color: #B48EAD\">31<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; prdata<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        intr<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_out<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_in<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_uclk_en;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_uclk_en;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/Register signals<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">8<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; bit_div;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; pre_scale;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">4<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; bit_mult;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_rx;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_clr;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_clr;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        parity_en;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        stop_en;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_en;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; uart_txdata;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> &#91; <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">&#93; uart_rxdata;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_uart_in;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk ) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><span style=\"color: #D8DEE9FF\"> <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_uart_in <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_uart_in <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> uart_in;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_tx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk ) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><span style=\"color: #D8DEE9FF\"> <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_tx_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_tx_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> tx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_rx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk ) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><span style=\"color: #D8DEE9FF\"> <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_rx_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_rx_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> rx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">uart_apb<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">u_apb<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">         .pclk         (pclk        )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.presetn      (presetn     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.penable      (penable     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.psel         (psel        )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.paddr        (paddr&#91;<\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">&#93;  )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.pwrite       (pwrite      )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.pwdata       (pwdata      )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.prdata       (prdata      )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.bit_div      (bit_div     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.pre_scale    (pre_scale   )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.bit_mult     (bit_mult    )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.tx_complete  (tx_complete )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.rx_complete  (rx_complete )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.tx_clr       (tx_clr      )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.rx_clr       (rx_clr      )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_en      (uart_en     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.parity_en    (parity_en   )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.stop_en      (stop_en     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_txdata  (uart_txdata )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_rxdata  (uart_rxdata )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    )<\/span><span style=\"color: #81A1C1\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">uart_tx_clkgen<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">u_tx_clkgen<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">         .pclk         (pclk        )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.presetn      (presetn     )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.bit_div      (bit_div     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.pre_scale    (pre_scale   )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.bit_mult     (bit_mult    )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.tx_uclk      (tx_uclk     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    )<\/span><span style=\"color: #81A1C1\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">uart_tx_ctrl<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">u_tx_ctrl<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">         .pclk         (pclk        )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.presetn      (presetn     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uclk_en      (tx_uclk_en  )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.parity_en    (parity_en   )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.stop_en      (stop_en     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_en      (uart_en     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_data    (uart_txdata )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.complete_clr (tx_clr      )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.complete     (tx_complete )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_out     (uart_out    )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    )<\/span><span style=\"color: #81A1C1\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">uart_rx_clkgen<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">u_rx_clkgen<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">         .pclk         (pclk        )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.presetn      (presetn     )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_rx      (uart_rx     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.bit_div      (bit_div     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.pre_scale    (pre_scale   )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.bit_mult     (bit_mult    )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.rx_uclk      (rx_uclk     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    )<\/span><span style=\"color: #81A1C1\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">uart_rx_ctrl<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">u_rx_ctrl<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">         .pclk         (pclk        )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.presetn      (presetn     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uclk_en      (rx_uclk_en  )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_in      (r_uart_in   )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.complete_clr (rx_clr      )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.parity_en    (parity_en   )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.stop_en      (stop_en     )<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_data    (uart_rxdata )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.complete     (rx_complete )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_rx      (uart_rx     )<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    )<\/span><span style=\"color: #81A1C1\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> tx_uclk_en <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\">  tx_uclk <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">~<\/span><span style=\"color: #D8DEE9FF\">r_tx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> rx_uclk_en <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">~<\/span><span style=\"color: #D8DEE9FF\">rx_uclk <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\">  r_rx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> intr       <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (tx_complete <\/span><span style=\"color: #81A1C1\">|<\/span><span style=\"color: #D8DEE9FF\"> rx_complete);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #81A1C1\">endmodule<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">\uc5ec\uae30\uc11c \uc8fc\uc758\ud560 \uc810\uc740, Rx controller\uc5d0 \ub4e4\uc5b4\uac08 input signal\uc740 \uc678\ubd80\uc5d0\uc11c \ub4e4\uc5b4\uc628 signal\uc744 \ubc14\ub85c \uc5f0\uacb0\ud55c \uac83\uc774 \uc544\ub2c8\ub77c pclk\ub85c \ucc44\uc11c 1 clk \ubbf8\ub8ec r_uart_in\uc744 \uc0ac\uc6a9\ud588\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><pre class=\"code-block-pro-copy-button-pre\" aria-hidden=\"true\"><textarea class=\"code-block-pro-copy-button-textarea\" tabindex=\"-1\" aria-hidden=\"true\" readonly>module uart (\n\n    ,input  wire        uart_in\n    \n);\n\n    reg         r_uart_in;\n    always @(negedge presetn or posedge pclk ) begin\n        if (!presetn) begin \n            r_uart_in &lt;= 1'b1;\n        end\n        else begin\n            r_uart_in &lt;= uart_in;\n        end\n    end\n\n    uart_rx_ctrl u_rx_ctrl (\n    \n        ,.uart_in      (r_uart_in   )<\/textarea><\/pre><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart (<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_in<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_uart_in;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk ) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><span style=\"color: #D8DEE9FF\"> <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_uart_in <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_uart_in <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> uart_in;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">uart_rx_ctrl<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">u_rx_ctrl<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        ,.uart_in      (r_uart_in   )<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">\uc774\ub294 \uc678\ubd80\uc5d0\uc11c \ub4e4\uc5b4\uc628 uart_in\uc744 \uc774 module\uc758 pclk\uc5d0 \ub9de\ucdb0\uc57c \ud558\uae30 \ub54c\ubb38\uc785\ub2c8\ub2e4(pclk sync\uc5d0 \ub9de\ucd94\ub294 \uacfc\uc815\uc774 \ud544\uc694\ud55c \uac81\ub2c8\ub2e4).<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\uc774\ub807\uac8c UART controller RTL design\uc744 \ud574\ubd24\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n<style>.kadence-column732_86962a-96 > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column732_86962a-96 > .kt-inside-inner-col,.kadence-column732_86962a-96 > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column732_86962a-96 > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column732_86962a-96 > .kt-inside-inner-col{flex-direction:column;}.kadence-column732_86962a-96 > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column732_86962a-96 > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column732_86962a-96{position:relative;}@media all and (max-width: 1024px){.kadence-column732_86962a-96 > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column732_86962a-96 > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column732_86962a-96\"><div class=\"kt-inside-inner-col\">\n<p class=\"wp-block-paragraph\"><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705<a href=\"https:\/\/rtlearner.com\/verilog-simulation-settings\/\">[Verilog] Simulation \ud658\uacbd \uc138\ud305 (EDA playground, Icarus verilog)<\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-1\/\">[Verilog] UART RTL design 1<\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-2\/\">[Verilog] UART RTL design 2<\/a><\/p>\n<\/div><\/div>\n\n\n\n<p class=\"wp-block-paragraph\">\ucc38\uace0: <a href=\"https:\/\/www.amebaiot.com\/en\/uart\/\" target=\"_blank\" rel=\"noopener\">Realtek UART<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>\uc774 \uae00\ub85c UART RTL design\uc744 \ub9c8\ubb34\ub9ac\ud558\uaca0\uc2b5\ub2c8\ub2e4. \uad00\ub828 \uae00 \u2705[Verilog] Simulation&#8230;<\/p>\n","protected":false},"author":1,"featured_media":743,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_kadence_starter_templates_imported_post":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[39],"tags":[40,99],"class_list":["post-732","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-verilog","tag-verilog","tag-apb-interface"],"_links":{"self":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/732","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/comments?post=732"}],"version-history":[{"count":4,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/732\/revisions"}],"predecessor-version":[{"id":1035,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/732\/revisions\/1035"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media\/743"}],"wp:attachment":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media?parent=732"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/categories?post=732"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/tags?post=732"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}<!-- This website is optimized by Airlift. Learn more: https://airlift.net. Template:. Learn more: https://airlift.net. Template: 6a588749d36f73a90a601ae0. Config Timestamp: 2026-07-16 07:24:54 UTC, Cached Timestamp: 2026-07-18 04:27:38 UTC, Optimization Time: 159.64ms -->