{"id":712,"date":"2024-09-25T17:17:24","date_gmt":"2024-09-25T08:17:24","guid":{"rendered":"https:\/\/rtlearner.com\/?p=712"},"modified":"2024-09-27T12:28:21","modified_gmt":"2024-09-27T03:28:21","slug":"verilog-uart-rtl-design-2","status":"publish","type":"post","link":"https:\/\/rtlearner.com\/en\/verilog-uart-rtl-design-2\/","title":{"rendered":"[Verilog] UART RTL design 2"},"content":{"rendered":"\n<p>\uc774\uc804 \uae00\uc5d0 \uc774\uc5b4\uc11c UART RTL design\uc744 \uacc4\uc18d\ud574 \ubcf4\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-table-of-content-nav.kb-table-of-content-id712_939189-4b .kb-table-of-content-wrap{padding-top:var(--global-kb-spacing-sm, 1.5rem);padding-right:var(--global-kb-spacing-sm, 1.5rem);padding-bottom:var(--global-kb-spacing-sm, 1.5rem);padding-left:var(--global-kb-spacing-sm, 1.5rem);box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kb-table-of-content-nav.kb-table-of-content-id712_939189-4b .kb-table-of-contents-title-wrap{padding-top:0px;padding-right:0px;padding-bottom:0px;padding-left:0px;}.kb-table-of-content-nav.kb-table-of-content-id712_939189-4b .kb-table-of-contents-title{font-weight:regular;font-style:normal;}.kb-table-of-content-nav.kb-table-of-content-id712_939189-4b .kb-table-of-content-wrap .kb-table-of-content-list{font-weight:regular;font-style:normal;margin-top:var(--global-kb-spacing-sm, 1.5rem);margin-right:0px;margin-bottom:0px;margin-left:0px;}@media all and (max-width: 767px){.kb-table-of-content-nav.kb-table-of-content-id712_939189-4b .kb-table-of-contents-title{font-size:var(--global-kb-font-size-md, 1.25rem);}.kb-table-of-content-nav.kb-table-of-content-id712_939189-4b .kb-table-of-content-wrap .kb-table-of-content-list{font-size:var(--global-kb-font-size-sm, 0.9rem);}}<\/style>\n\n<style>.kadence-column712_9c6570-1e > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column712_9c6570-1e > .kt-inside-inner-col,.kadence-column712_9c6570-1e > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column712_9c6570-1e > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column712_9c6570-1e > .kt-inside-inner-col{flex-direction:column;}.kadence-column712_9c6570-1e > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column712_9c6570-1e > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column712_9c6570-1e{position:relative;}@media all and (max-width: 1024px){.kadence-column712_9c6570-1e > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column712_9c6570-1e > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column712_9c6570-1e\"><div class=\"kt-inside-inner-col\">\n<p><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-simulation-settings\/\">[Verilog] Simulation \ud658\uacbd \uc138\ud305 (EDA playground, Icarus verilog)<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-1\/\">[Verilog] UART RTL design 1<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-3\/\">[Verilog] UART RTL design 3<\/a><\/p>\n<\/div><\/div>\n\n\n\n<h2 class=\"wp-block-heading\">UART RTL design<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">CLK gen RTL design<\/h3>\n\n\n\n<p>\ub2e4\uc74c\uc73c\ub85c baud rate\ub97c \uc124\uc815\ud574 \uc8fc\ub294 clk gen\uc744 \uc124\uacc4\ud574 \ubd05\uc2dc\ub2e4. Block diagram\uc744 \ubcf4\uba74 Tx\/Rx\uc5d0 \uac01\uac01\uc758 clk gen\uc774 \uc788\ub294\ub370, \uae30\ub2a5\uc740 \ube44\uc2b7\ud558\uae30 \ub54c\ubb38\uc5d0 tx clk gen\uc744 \uba3c\uc800 \uc124\uacc4\ud574 \ubcf4\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"module uart_tx_clkgen (\n     input  wire        presetn\n    ,input  wire        pclk\n\n    ,input  wire [ 8:0] bit_div\n    ,input  wire [ 2:0] pre_scale\n    ,input  wire [ 4:0] bit_mult\n\n    ,output wire        tx_uclk\n);\n\n    reg         r_uclk;\n    reg  [ 8:0] r_prescale;\n    reg  [13:0] r_divisor_1;\n    reg  [22:0] r_divisor_2;\n    reg  [21:0] r_dividercnt;\n\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn)    r_prescale  &lt;= 9'd0;\n        else begin\n            case (pre_scale)\n                3'd0   : r_prescale &lt;= 9'd2  ;\n                3'd1   : r_prescale &lt;= 9'd4  ;\n                3'd2   : r_prescale &lt;= 9'd8  ;\n                3'd3   : r_prescale &lt;= 9'd16 ;\n                3'd4   : r_prescale &lt;= 9'd32 ;\n                3'd5   : r_prescale &lt;= 9'd64 ;\n                3'd6   : r_prescale &lt;= 9'd128;\n                3'd7   : r_prescale &lt;= 9'd256;\n                default: r_prescale &lt;= r_prescale;\n            endcase\n        end\n    end\n\n    \/\/r_divisor_1  =  { 2^(pre_scale+1) x (bit_mult + 1) } ]\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn) r_divisor_1 &lt;= 14'd0; \n        else          r_divisor_1 &lt;= r_prescale * (bit_mult + 'b1);\n    end\n\n    \/\/r_divisor_2  =  [ (bit_div) x  { 2^(pre_scale+1) x (bit_mult + 1) } ]\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn) r_divisor_2 &lt;= 23'd0; \n        else          r_divisor_2 &lt;= r_divisor_1 * bit_div;\n    end\n\n    \/\/half cycle of serial clock = r_divisor_2 \/ 2\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn)                          r_dividercnt &lt;= 22'd0; \n        else if (r_dividercnt !=  r_divisor_2) r_dividercnt &lt;= (r_dividercnt + 'b1);\n        else                                   r_dividercnt &lt;= 22'd0; \n    end\n\n    wire [22:0] r_divisor_2_half;\n    assign      r_divisor_2_half = r_divisor_2 &gt;&gt; 1;\n\n    \/\/serial clock generation\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn)                             r_uclk &lt;= 'b0;\n        else if (r_dividercnt &lt; r_divisor_2_half) r_uclk &lt;= 'b0;\n        else                                      r_uclk &lt;= 'b1;\n    end\n\n    assign tx_uclk = r_uclk;\n\nendmodule\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart_tx_clkgen (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        presetn<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pclk<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">8<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] bit_div<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] pre_scale<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">4<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] bit_mult<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_uclk<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">8<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_prescale;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [<\/span><span style=\"color: #B48EAD\">13<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_divisor_1;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [<\/span><span style=\"color: #B48EAD\">22<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_divisor_2;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [<\/span><span style=\"color: #B48EAD\">21<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_dividercnt;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)    r_prescale  <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (pre_scale)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d0<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d2<\/span><span style=\"color: #D8DEE9FF\">  ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d1<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d4<\/span><span style=\"color: #D8DEE9FF\">  ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d2<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d8<\/span><span style=\"color: #D8DEE9FF\">  ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d3<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d16<\/span><span style=\"color: #D8DEE9FF\"> ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d4<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d32<\/span><span style=\"color: #D8DEE9FF\"> ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d5<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d64<\/span><span style=\"color: #D8DEE9FF\"> ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d6<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d128<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">3&#39;d7<\/span><span style=\"color: #D8DEE9FF\">   : r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">9&#39;d256<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\">: r_prescale <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_prescale;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/r_divisor_1  =  { 2^(pre_scale+1) x (bit_mult + 1) } ]<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) r_divisor_1 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">14&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">          r_divisor_1 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_prescale <\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\"> (bit_mult <\/span><span style=\"color: #81A1C1\">+<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/r_divisor_2  =  [ (bit_div) x  { 2^(pre_scale+1) x (bit_mult + 1) } ]<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) r_divisor_2 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">23&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">          r_divisor_2 <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_divisor_1 <\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\"> bit_div;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/half cycle of serial clock = r_divisor_2 \/ 2<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)                          r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">22&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (r_dividercnt <\/span><span style=\"color: #81A1C1\">!=<\/span><span style=\"color: #D8DEE9FF\">  r_divisor_2) r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> (r_dividercnt <\/span><span style=\"color: #81A1C1\">+<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                                   r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">22&#39;d0<\/span><span style=\"color: #D8DEE9FF\">; <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [<\/span><span style=\"color: #B48EAD\">22<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_divisor_2_half;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\">      r_divisor_2_half <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_divisor_2 <\/span><span style=\"color: #81A1C1\">&gt;&gt;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/serial clock generation<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)                             r_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (r_dividercnt <\/span><span style=\"color: #81A1C1\">&lt;<\/span><span style=\"color: #D8DEE9FF\"> r_divisor_2_half) r_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                                      r_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> tx_uclk <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_uclk;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #81A1C1\">endmodule<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>Baud rate\uc758 \uc124\uc815 \uc218\uc2dd\uc740 \ub2e4\uc74c\uacfc \uac19\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"has-text-align-center\">F<sub>baud<\/sub> = F<sub>pclk<\/sub> \/ [ 2 ^ ( pre_scale + 1 ) x { bit_div x ( bit_mult + 1 ) } ]<\/p>\n\n\n\n<p>Module\uc5d0 \uc0ac\uc6a9\ub418\ub294 pclk\uc758 \uc8fc\uae30\uc640 register setting\uc5d0 \ub530\ub77c baud rate\uac00 \uacb0\uc815\ub429\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-image712_8f2fa8-67.kb-image-is-ratio-size, .kb-image712_8f2fa8-67 .kb-image-is-ratio-size{max-width:600px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_8f2fa8-67.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_8f2fa8-67 .kb-image-is-ratio-size{align-self:unset;}.kb-image712_8f2fa8-67 figure{max-width:600px;}.kb-image712_8f2fa8-67 .image-is-svg, .kb-image712_8f2fa8-67 .image-is-svg img{width:100%;}.kb-image712_8f2fa8-67 .kb-image-has-overlay:after{opacity:0.3;}.kb-image712_8f2fa8-67 img.kb-img, .kb-image712_8f2fa8-67 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image712_8f2fa8-67.kb-image-is-ratio-size, .kb-image712_8f2fa8-67 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image712_8f2fa8-67 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image712_8f2fa8-67\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/bmfDZ2\/btsJda6FqOQ\/EGg8EOkKUyDjn9OoXUmIYk\/img.png\" alt=\"Baud rate setting\" class=\"kb-img\"\/><figcaption>Baud rate setting<\/figcaption><\/figure><\/div>\n\n\n\n<p>\uc774\ub807\uac8c \uc0dd\uc131\ub41c clock(uclk)\uc744 Tx controller\uc5d0\uc11c \uc0ac\uc6a9\ud558\uac8c \ub429\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    always @(negedge presetn or posedge uclk) begin\n        if   ~~~~\n        else ~~~~\n    end\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> uclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\">   <\/span><span style=\"color: #81A1C1\">~~~~<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">~~~~<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\ud558\uc9c0\ub9cc \uc774\ub807\uac8c \uc124\uacc4\ud558\uba74 \ud55c IP\uc5d0 \ub450 clock domain\uc73c\ub85c \ub098\ub258\uae30 \ub54c\ubb38\uc5d0 SDC(Synopsys Design Constraints) setting \ud558\ub294 \ub370 \uc5b4\ub824\uc6c0\uc774 \uc788\uc2b5\ub2c8\ub2e4. \ud569\uc131\uc744 \uc704\ud574\uc11c\ub294 constraint \ud30c\uc77c\uc5d0 clock\uc5d0 \ub300\ud55c \uc815\ubcf4\ub97c \ubaa8\ub450 \uc785\ub825\ud574\uc57c \ud558\ub294\ub370, uclk\uc744 \uc0ac\uc6a9\ud558\uba74 \uadf8\uc5d0 \ub300\ud55c \uc124\uc815\uc744 \ucd94\uac00\ub85c \uc785\ub825\ud574\uc57c \ud569\ub2c8\ub2e4. \uacb0\ub860\uc801\uc73c\ub85c, \ud55c IP\uc5d0\ub294 \ud55c clock\uc73c\ub85c\ub9cc \uc791\ub3d9\ud558\ub294 \uac83\uc774 \uc88b\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-image712_8ef6b2-c5.kb-image-is-ratio-size, .kb-image712_8ef6b2-c5 .kb-image-is-ratio-size{max-width:650px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_8ef6b2-c5.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_8ef6b2-c5 .kb-image-is-ratio-size{align-self:unset;}.kb-image712_8ef6b2-c5 figure{max-width:650px;}.kb-image712_8ef6b2-c5 .image-is-svg, .kb-image712_8ef6b2-c5 .image-is-svg img{width:100%;}.kb-image712_8ef6b2-c5 .kb-image-has-overlay:after{opacity:0.3;}.kb-image712_8ef6b2-c5 img.kb-img, .kb-image712_8ef6b2-c5 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image712_8ef6b2-c5.kb-image-is-ratio-size, .kb-image712_8ef6b2-c5 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image712_8ef6b2-c5 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image712_8ef6b2-c5\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/u6kQl\/btsJoPAZOyP\/kHiZYqpOMlKS3MWr9XTak1\/img.png\" alt=\"uclk \uc0ac\uc6a9 \uc2dc clock domain\" class=\"kb-img\"\/><figcaption>uclk \uc0ac\uc6a9 \uc2dc clock domain<\/figcaption><\/figure><\/div>\n\n\n\n<h4 class=\"wp-block-heading\">uclk_en<\/h4>\n\n\n\n<p>\uadf8\ub798\uc11c uclk enable signal(uclk posedge signal)\uc744 \ub9cc\ub4e4\uc5b4 \uc124\uacc4\ub97c \uc9c4\ud589\ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    wire        tx_uclk;\n    wire        tx_uclk_en;\n    \n    reg         r_tx_uclk;\n    always @(negedge presetn or posedge pclk) begin\n        if (!presetn) begin \n            r_tx_uclk &lt;= 1'b0;\n        end\n        else begin\n            r_tx_uclk &lt;= tx_uclk;\n        end\n    end\n\n    assign tx_uclk_en =  tx_uclk &amp; ~r_tx_uclk;\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_uclk_en;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_tx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><span style=\"color: #D8DEE9FF\"> <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_tx_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            r_tx_uclk <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> tx_uclk;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> tx_uclk_en <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\">  tx_uclk <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">~<\/span><span style=\"color: #D8DEE9FF\">r_tx_uclk;<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\uc774 logic\uc744 \ud1b5\ud574 1 pclk\uc758 uclk_en signal\uc744 \ub9cc\ub4e4 \uc218 \uc788\uace0, \uc774\ub97c Tx controller\uc5d0 \uc0ac\uc6a9\ud558\uba74 \ub429\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-image712_e480aa-17.kb-image-is-ratio-size, .kb-image712_e480aa-17 .kb-image-is-ratio-size{max-width:550px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_e480aa-17.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_e480aa-17 .kb-image-is-ratio-size{align-self:unset;}.kb-image712_e480aa-17 figure{max-width:550px;}.kb-image712_e480aa-17 .image-is-svg, .kb-image712_e480aa-17 .image-is-svg img{width:100%;}.kb-image712_e480aa-17 .kb-image-has-overlay:after{opacity:0.3;}.kb-image712_e480aa-17 img.kb-img, .kb-image712_e480aa-17 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image712_e480aa-17.kb-image-is-ratio-size, .kb-image712_e480aa-17 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image712_e480aa-17 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image712_e480aa-17\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/ckuU94\/btsJnKAne1c\/SoFeTj3fgxEGm5NKpugSwK\/img.png\" alt=\"uclk_en signal\" class=\"kb-img\"\/><figcaption>uclk_en signal<\/figcaption><\/figure><\/div>\n\n\n\n<h3 class=\"wp-block-heading\">Tx controller RTL design<\/h3>\n\n\n\n<p>Tx controller\ub97c \uc124\uacc4\ud558\uae30 \uc804\uc5d0, \uba3c\uc800 FSM(finite-state machine)\uc5d0 \ub300\ud574 \uc54c\uc544\ubd05\uc2dc\ub2e4.<\/p>\n\n\n\n<p>\ud1b5\uc2e0 Protocol\uc740 &#8216;\uc57d\uc18d&#8217;\uc785\ub2c8\ub2e4. \uc0c1\ud638 \ud569\uc758\ub41c \uc21c\uc11c\ub300\ub85c \ub370\uc774\ud130\ub97c \uc8fc\uace0\ubc1b\uae30 \ub54c\ubb38\uc5d0 \uc2e0\ub8b0\uc131 \uc788\uac8c \ud1b5\uc2e0\ud560 \uc218 \uc788\uace0, \uadf8\ub807\uae30 \ub54c\ubb38\uc5d0 controller\ub294 protocol\ub300\ub85c \ud1b5\uc2e0\uc744 \uc9c4\ud589\ud574\uc57c \ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<p>FSM\uc740 \uc720\ud55c\ud55c state\ub85c \ud1b5\uc2e0\uc744 \uc9c4\ud589\ud560 \ub54c, \uac01\uac01\uc758 state\uc758 \uc0c1\ud0dc\ub098 \uc785\/\ucd9c\ub825, \ub2e4\uc74c state\ub85c \ub118\uc5b4\uac00\uae30 \uc704\ud55c \uc870\uac74 \ub4f1\uc744 \uc815\uc758\ud55c \ubaa8\ub378\uc785\ub2c8\ub2e4. Protocol\uc758 state\ub97c \ud655\uc778\ud574 \ubcfc\uae4c\uc694?<\/p>\n\n\n<style>.kb-image712_08efb1-85.kb-image-is-ratio-size, .kb-image712_08efb1-85 .kb-image-is-ratio-size{max-width:240px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_08efb1-85.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_08efb1-85 .kb-image-is-ratio-size{align-self:unset;}.kb-image712_08efb1-85 figure{max-width:240px;}.kb-image712_08efb1-85 .image-is-svg, .kb-image712_08efb1-85 .image-is-svg img{width:100%;}.kb-image712_08efb1-85 .kb-image-has-overlay:after{opacity:0.3;}.kb-image712_08efb1-85 img.kb-img, .kb-image712_08efb1-85 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image712_08efb1-85.kb-image-is-ratio-size, .kb-image712_08efb1-85 .kb-image-is-ratio-size{max-width:240px;width:100%;}.kb-image712_08efb1-85 figure{max-width:240px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image712_08efb1-85\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/Xp4Tr\/btsJh9G2MEX\/1ar4xKY7CYkbsDcfNrmjtK\/img.png\" alt=\"Tx controller FSM\" class=\"kb-img\"\/><figcaption>Tx controller FSM<\/figcaption><\/figure><\/div>\n\n\n\n<p>\ud1b5\uc2e0\ud558\uc9c0 \uc54a\uc744 \ub54c\ub294 IDLE \uc0c1\ud0dc\uc785\ub2c8\ub2e4. Tx controller\uac00 \ud1b5\uc2e0\uc744 \uc2dc\uc791\ud558\uba74 START \uc0c1\ud0dc\uac00 \ub418\uace0 1 uclk \ub4a4\uc5d0 8-bit\uc758 \ub370\uc774\ud130\ub97c \ub0b4\ubcf4\ub0c5\ub2c8\ub2e4. \ub9cc\uc57d parity\ub97c \uc124\uc815\ud588\ub2e4\uba74 1-bit\uc758 parity bit\uac00 \ub098\uac00\uace0, \uadf8\ub807\uc9c0 \uc54a\uc73c\uba74 \ubc14\ub85c STOP_1\ub85c \ub118\uc5b4\uac11\ub2c8\ub2e4. \ud574\ub2f9 \ud1b5\uc2e0\uc744 2-stop\uc73c\ub85c \uc124\uc815\ud588\ub2e4\uba74 STOP_1\uc5d0\uc11c STOP_2\ub97c \uac70\uccd0 IDLE \uc0c1\ud0dc\uac00 \ub418\uace0, \uc124\uc815\ud558\uc9c0 \uc54a\uc558\ub2e4\uba74 \uadf8\ub0e5 IDLE \uc0c1\ud0dc\uac00 \ub429\ub2c8\ub2e4.<\/p>\n\n\n\n<p>\uadf8\ub7ec\uba74 \uc774\ub97c \uae30\ubc18\uc73c\ub85c Tx controller\ub97c \uc124\uacc4\ud574 \ubd05\uc2dc\ub2e4. \uba3c\uc800 input output port \uc120\uc5c5\uc785\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"module uart_tx_ctrl (\n     input  wire        pclk\n    ,input  wire        presetn\n\n    ,input  wire        uclk_en\n\n    ,input  wire [ 7:0] uart_data\n    ,input  wire        uart_en\n    ,input  wire        complete_clr\n    ,input  wire        parity_en\n    ,input  wire        stop_en\n\n    ,output wire        complete\n\n    ,output wire        uart_out\n);\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart_tx_ctrl (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pclk<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        presetn<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uclk_en<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] uart_data<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        complete_clr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        parity_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        stop_en<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        complete<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_out<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\uc5ec\uae30\uc11c complete\ub294 1-byte transfer\uac00 \ub05d\ub098\uba74 CPU\uc5d0 intr\ub85c \uc54c\ub9ac\uae30 \uc704\ud55c signal\uc785\ub2c8\ub2e4. \ub2e4\uc74c\uc73c\ub85c \uc790\ub8cc\ud615 \uc120\uc5b8\uc785\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    \/\/===================================================================\n    \/\/ Local Parameters\n    \/\/===================================================================\n    localparam IDLE        = 3'h0,\n               START       = 3'h1,\n               DATA        = 3'h2,\n               PARITY      = 3'h3,\n               STOP        = 3'h4,\n               TRANSFINISH = 3'h5;\n\n    reg  [ 2:0] r_cur_st;\n    reg  [ 2:0] r_nxt_st;\n    reg  [ 7:0] r_bitcnt;\n\n    reg         r_uart;\n    reg         r_complete;\n    reg  [ 7:0] r_shift;    \/\/shift register\n\n    wire        data_end;   \/\/DATA state end\n    assign data_end = (r_bitcnt == 8'h8);\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Local Parameters<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">localparam<\/span><span style=\"color: #D8DEE9FF\"> IDLE        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h0<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               START       <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h1<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               DATA        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h2<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               PARITY      <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h3<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               STOP        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h4<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               TRANSFINISH <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h5<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_cur_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_nxt_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_bitcnt;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_uart;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_shift;    <\/span><span style=\"color: #616E88\">\/\/shift register<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        data_end;   <\/span><span style=\"color: #616E88\">\/\/DATA state end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> data_end <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (r_bitcnt <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h8<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\uac01\uac01\uc758 \uc790\ub8cc\ud615\uc5d0 \ub300\ud55c \uc124\uba85\uc740 \uc774\uc5b4\uc11c \uacc4\uc18d\ud558\uaca0\uc2b5\ub2c8\ub2e4. \ub2e4\uc74c\uc73c\ub85c FSM \uc124\uacc4\uc785\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    \/\/cur_st\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)          r_cur_st &lt;= IDLE;\n        else if (complete_clr) r_cur_st &lt;= IDLE;\n        else                   r_cur_st &lt;= r_nxt_st;\n    end\n\n    \/\/FSM\n    always @(*) begin\n        case (r_cur_st)\n            IDLE        : begin\n                if (uart_en &amp; uclk_en) begin\n                     r_nxt_st &lt;= START;\n                end\n                else r_nxt_st &lt;= IDLE;\n            end\n            START       : begin\n                if (uclk_en) begin\n                     r_nxt_st &lt;= DATA;\n                end\n                else r_nxt_st &lt;= START;\n            end\n            DATA        : begin\n                if (data_end &amp; parity_en) begin\n                     r_nxt_st &lt;= PARITY;\n                end\n                else if (data_end &amp; !parity_en &amp; stop_en) begin\n                     r_nxt_st &lt;= STOP;\n                end\n                else if (data_end &amp; !parity_en &amp; !stop_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= DATA;\n            end\n            PARITY      : begin\n                if (stop_en &amp; uclk_en) begin\n                     r_nxt_st &lt;= STOP;\n                end\n                else if (uclk_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= PARITY;\n            end\n            STOP        : begin\n                if (uclk_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= STOP;\n            end\n            TRANSFINISH : begin\n                if (complete_clr) begin\n                     r_nxt_st &lt;= IDLE;\n                end\n                else r_nxt_st &lt;= TRANSFINISH;\n            end\n            default     : begin\n                r_nxt_st &lt;= IDLE;\n            end\n        endcase\n    end\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/cur_st<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)          r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr) r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                   r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/FSM<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\">) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            IDLE        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uart_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> START;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            START       : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> START;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            DATA        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> parity_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> PARITY;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">parity_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> stop_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">parity_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">stop_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            PARITY      : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (stop_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> PARITY;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            STOP        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            TRANSFINISH : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\">     : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\uc5ec\uae30\uc11c TRANSFINISH\uac00 stop_1 state\uc774\uace0, STOP\uc774 stop_2 state\ub77c\uace0 \uc774\ud574\ud558\uc2dc\uba74 \ub418\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<p>\uc65c \uadf8\ub7f0\uc9c0 \ubaa8\ub974\uaca0\ub294\ub370, \ub300\ubd80\ubd84\uc758 IP\uc740 nxt_st(next state)\ub97c 1 clock \ubc00\uc5b4\uc11c cur_st(current state)\ub85c \uc4f0\ub354\ub77c\uace0\uc694;;; \uc774\uc720\ub97c \uc544\uc2dc\ub294 \ubd84 \uba54\uc77c\ub85c \uc54c\ub824\uc8fc\uc2dc\uba74 \u3160\u3160.<\/p>\n\n\n\n<p>\ub2e4\uc74c\uc73c\ub85c bitcnt(bit counter) \uc124\uacc4\uc785\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    \/\/BITCNT\n    wire data_st;\n    assign data_st = (r_cur_st == DATA);\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_bitcnt &lt;= 8'h0;\n        else if (complete_clr)      r_bitcnt &lt;= 8'h0;\n        else if (data_st &amp; uclk_en) r_bitcnt &lt;= (r_bitcnt + 1);\n        else                        r_bitcnt &lt;= r_bitcnt;\n    end\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/BITCNT<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> data_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> data_st <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> DATA);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr)      r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_st <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> (r_bitcnt <\/span><span style=\"color: #81A1C1\">+<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_bitcnt;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>bitcnt\ub294 DATA state\uc5d0\uc11c 8-bit \ub3d9\uc548 tx \ud560 data\ub97c shift \ud558\uba74\uc11c 1-bit \uc529 transfer \ud558\uae30 \uc704\ud574 \uc0ac\uc6a9\ud569\ub2c8\ub2e4. \uadf8\ub7ec\uba74 \ubc14\ub85c shift register \uc124\uacc4\ub97c \ud655\uc778\ud574 \ubcfc\uae4c\uc694?<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    \/\/shift reg\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_shift &lt;= 8'h0;\n        else if (data_st) begin\n            if (uclk_en)            r_shift &lt;= {1'b0,r_shift[7:1]};\n            else                    r_shift &lt;= r_shift;\n        end\n        else                        r_shift &lt;= uart_data;\n    end\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/shift reg<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_st) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en)            r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> {<\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">,r_shift[<\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">]};<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                    r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_shift;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> uart_data;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\uc774\ub807\uac8c \uc124\uacc4\ud558\uba74 APB register\uc5d0\uc11c \ub4e4\uc5b4\uc628 data\uac00 1-bit \uc529 shift \ub418\uba74\uc11c r_shift\uc5d0 \uc800\uc7a5\ub429\ub2c8\ub2e4. \uadf8\ub7ec\uba74 r_shift\uac00 \uc5b4\ub5bb\uac8c output\uc73c\ub85c \ub098\uac00\ub294 \uac78\uae4c\uc694?<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    \/\/UART tx\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn) r_uart &lt;= 1'b1;\n        else begin\n            case (r_cur_st)\n                IDLE        : begin\n                    if (uart_en &amp; uclk_en) begin\n                         r_uart &lt;= 1'b0;\n                    end\n                    else r_uart &lt;= 1'b1;\n                end\n                START       : begin\n                    if (uclk_en) begin\n                         r_uart &lt;= r_uart;\n                    end\n                    else r_uart &lt;= r_uart;\n                end\n                DATA        : begin\n                    r_uart &lt;= r_shift[0]; \/\/shift register\n                end\n                PARITY      : begin\n                    r_uart &lt;= 1'b0;       \/\/\uc218\uc815 \ud544\uc694 (parity)\n                end\n                STOP        : begin\n                    r_uart &lt;= 1'b1;\n                end\n                TRANSFINISH : begin\n                    r_uart &lt;= 1'b1;\n                end\n                default     : begin\n                    r_uart &lt;= 1'b1;\n                end\n            endcase\n        end\n    end\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/UART tx<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                IDLE        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uart_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                         r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                START       : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                         r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_uart;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_uart;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                DATA        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_shift[<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">]; <\/span><span style=\"color: #616E88\">\/\/shift register<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                PARITY      : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;       <\/span><span style=\"color: #616E88\">\/\/\uc218\uc815 \ud544\uc694 (parity)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                STOP        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                TRANSFINISH : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\">     : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\uc218\uc815\uc774 \ud544\uc694\ud55c \uacf3\uc774 \uc788\ub294\ub370, parity\uac00 enable \ub3fc \uc788\uc73c\uba74 \uacc4\uc0b0\ub41c parity\uac00 output\uc73c\ub85c \ub098\uac00\ub294 \uac81\ub2c8\ub2e4. parity \uacc4\uc0b0\uc740 \uc9c1\uc811 \ud574\ubcf4\uc2dc\ub294 \uac83\ub3c4 \uc88b\uc744 \uac83 \uac19\ub124\uc694!! (\uadc0\ucc2e\uc544\uc11c \ud558\uc9c0 \uc54a\uc740 \uac74 \uc548 \ube44\ubc00;;;;;)<\/p>\n\n\n\n<p>\ub9c8\uc9c0\ub9c9\uc73c\ub85c complete intr\uc640 output port assign\uc785\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"    \/\/complete intr\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_complete &lt;= 1'b0;\n        else if (complete_clr)      r_complete &lt;= 1'b0;\n        else if ((r_cur_st == TRANSFINISH) &amp; uclk_en) begin\n                                    r_complete &lt;= 1'b1;\n        end\n        else                        r_complete &lt;= r_complete;\n    end\n\n    assign complete = r_complete;\n    assign uart_out = r_uart;\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/complete intr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr)      r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> ((r_cur_st <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH) <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                                    r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> complete <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> uart_out <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_uart;<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\ud55c \ubc88 \uc804\uccb4\uc801\uc73c\ub85c \ud655\uc778\ud574 \ubcfc\uae4c\uc694?<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"module uart_tx_ctrl (\n     input  wire        pclk\n    ,input  wire        presetn\n\n    ,input  wire        uclk_en\n\n    ,input  wire [ 7:0] uart_data\n    ,input  wire        uart_en\n    ,input  wire        complete_clr\n    ,input  wire        parity_en\n    ,input  wire        stop_en\n\n    ,output wire        complete\n\n    ,output wire        uart_out\n);\n\n    \/\/===================================================================\n    \/\/ Local Parameters\n    \/\/===================================================================\n    localparam IDLE        = 3'h0,\n               START       = 3'h1,\n               DATA        = 3'h2,\n               PARITY      = 3'h3,\n               STOP        = 3'h4,\n               TRANSFINISH = 3'h5;\n\n    reg  [ 2:0] r_cur_st;\n    reg  [ 2:0] r_nxt_st;\n    reg  [ 7:0] r_bitcnt;\n\n    reg         r_uart;\n    reg         r_complete;\n    reg  [ 7:0] r_shift;    \/\/shift register\n\n    wire        data_end;   \/\/DATA state end\n\t\n\t\/\/cur_st\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)          r_cur_st &lt;= IDLE;\n        else if (complete_clr) r_cur_st &lt;= IDLE;\n        else                   r_cur_st &lt;= r_nxt_st;\n    end\n\n    \/\/FSM\n    always @(*) begin\n        case (r_cur_st)\n            IDLE        : begin\n                if (uart_en &amp; uclk_en) begin\n                     r_nxt_st &lt;= START;\n                end\n                else r_nxt_st &lt;= IDLE;\n            end\n            START       : begin\n                if (uclk_en) begin\n                     r_nxt_st &lt;= DATA;\n                end\n                else r_nxt_st &lt;= START;\n            end\n            DATA        : begin\n                if (data_end &amp; parity_en) begin\n                     r_nxt_st &lt;= PARITY;\n                end\n                else if (data_end &amp; !parity_en &amp; stop_en) begin\n                     r_nxt_st &lt;= STOP;\n                end\n                else if (data_end &amp; !parity_en &amp; !stop_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= DATA;\n            end\n            PARITY      : begin\n                if (stop_en &amp; uclk_en) begin\n                     r_nxt_st &lt;= STOP;\n                end\n                else if (uclk_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= PARITY;\n            end\n            STOP        : begin\n                if (uclk_en) begin\n                     r_nxt_st &lt;= TRANSFINISH;\n                end\n                else r_nxt_st &lt;= STOP;\n            end\n            TRANSFINISH : begin\n                if (complete_clr) begin\n                     r_nxt_st &lt;= IDLE;\n                end\n                else r_nxt_st &lt;= TRANSFINISH;\n            end\n            default     : begin\n                r_nxt_st &lt;= IDLE;\n            end\n        endcase\n    end\n\n    \/\/BITCNT\n    wire data_st;\n    assign data_st = (r_cur_st == DATA);\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_bitcnt &lt;= 8'h0;\n        else if (complete_clr)      r_bitcnt &lt;= 8'h0;\n        else if (data_st &amp; uclk_en) r_bitcnt &lt;= (r_bitcnt + 1);\n        else                        r_bitcnt &lt;= r_bitcnt;\n    end\n\n    \/\/shift reg\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_shift &lt;= 8'h0;\n        else if (data_st) begin\n            if (uclk_en)            r_shift &lt;= {1'b0,r_shift[7:1]};\n            else                    r_shift &lt;= r_shift;\n        end\n        else                        r_shift &lt;= uart_data;\n    end\n\n    \/\/UART tx\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn) r_uart &lt;= 1'b1;\n        else begin\n            case (r_cur_st)\n                IDLE        : begin\n                    if (uart_en &amp; uclk_en) begin\n                         r_uart &lt;= 1'b0;\n                    end\n                    else r_uart &lt;= 1'b1;\n                end\n                START       : begin\n                    if (uclk_en) begin\n                         r_uart &lt;= r_uart;\n                    end\n                    else r_uart &lt;= r_uart;\n                end\n                DATA        : begin\n                    r_uart &lt;= r_shift[0]; \/\/shift register\n                end\n                PARITY      : begin\n                    r_uart &lt;= 1'b0;       \/\/\uc218\uc815 \ud544\uc694 (parity)\n                end\n                STOP        : begin\n                    r_uart &lt;= 1'b1;\n                end\n                TRANSFINISH : begin\n                    r_uart &lt;= 1'b1;\n                end\n                default     : begin\n                    r_uart &lt;= 1'b1;\n                end\n            endcase\n        end\n    end\n\n    \/\/complete intr\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)               r_complete &lt;= 1'b0;\n        else if (complete_clr)      r_complete &lt;= 1'b0;\n        else if ((r_cur_st == TRANSFINISH) &amp; uclk_en) begin\n                                    r_complete &lt;= 1'b1;\n        end\n        else                        r_complete &lt;= r_complete;\n    end\n\n    assign data_end = (r_bitcnt == 8'h8);\n    assign complete = r_complete;\n    assign uart_out = r_uart;\n\nendmodule\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart_tx_ctrl (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pclk<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        presetn<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uclk_en<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] uart_data<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        complete_clr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        parity_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        stop_en<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        complete<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_out<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Local Parameters<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">localparam<\/span><span style=\"color: #D8DEE9FF\"> IDLE        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h0<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               START       <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h1<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               DATA        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h2<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               PARITY      <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h3<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               STOP        <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h4<\/span><span style=\"color: #D8DEE9FF\">,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">               TRANSFINISH <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">3&#39;h5<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_cur_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_nxt_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_bitcnt;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_uart;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_shift;    <\/span><span style=\"color: #616E88\">\/\/shift register<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        data_end;   <\/span><span style=\"color: #616E88\">\/\/DATA state end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">\t<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">\t<\/span><span style=\"color: #616E88\">\/\/cur_st<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)          r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr) r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                   r_cur_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/FSM<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\">) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            IDLE        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uart_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> START;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            START       : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> START;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            DATA        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> parity_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> PARITY;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">parity_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> stop_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_end <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">parity_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">stop_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            PARITY      : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (stop_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> PARITY;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            STOP        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> STOP;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            TRANSFINISH : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                     r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\">     : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                r_nxt_st <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> IDLE;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/BITCNT<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> data_st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> data_st <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> DATA);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr)      r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_st <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> (r_bitcnt <\/span><span style=\"color: #81A1C1\">+<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_bitcnt <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_bitcnt;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/shift reg<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (data_st) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en)            r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> {<\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">,r_shift[<\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">]};<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                    r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_shift;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_shift <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> uart_data;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/UART tx<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn) r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (r_cur_st)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                IDLE        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uart_en <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                         r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                START       : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                         r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_uart;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_uart;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                DATA        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_shift[<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">]; <\/span><span style=\"color: #616E88\">\/\/shift register<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                PARITY      : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;       <\/span><span style=\"color: #616E88\">\/\/\uc218\uc815 \ud544\uc694 (parity)<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                STOP        : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                TRANSFINISH : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\">     : <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                    r_uart <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/complete intr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)               r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (complete_clr)      r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> ((r_cur_st <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> TRANSFINISH) <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> uclk_en) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                                    r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b1<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">                        r_complete <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> data_end <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (r_bitcnt <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h8<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> complete <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_complete;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> uart_out <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_uart;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #81A1C1\">endmodule<\/span><\/span><\/code><\/pre><\/div>\n\n\n<style>.kb-image712_5f157a-bc.kb-image-is-ratio-size, .kb-image712_5f157a-bc .kb-image-is-ratio-size{max-width:580px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_5f157a-bc.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image712_5f157a-bc .kb-image-is-ratio-size{align-self:unset;}.kb-image712_5f157a-bc figure{max-width:580px;}.kb-image712_5f157a-bc .image-is-svg, .kb-image712_5f157a-bc .image-is-svg img{width:100%;}.kb-image712_5f157a-bc .kb-image-has-overlay:after{opacity:0.3;}.kb-image712_5f157a-bc img.kb-img, .kb-image712_5f157a-bc .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image712_5f157a-bc.kb-image-is-ratio-size, .kb-image712_5f157a-bc .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image712_5f157a-bc figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image712_5f157a-bc\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/u7p6d\/btsJiNcqhU3\/XMema9PNscbo4geuS8UBkK\/img.png\" alt=\"Simulation result\" class=\"kb-img\"\/><figcaption>Simulation result<\/figcaption><\/figure><\/div>\n\n\n\n<p>\uc704 \uc2dc\ubbac\ub808\uc774\uc158 \uacb0\uacfc\ub294 Tx data\uac00 0xA, stop_en\uacfc parity_en\uc774 \ub458 \ub2e4 \uc124\uc815\ub418\uc9c0 \uc54a\uc558\uc744 \ub54c\uc758 \uacb0\uacfc\uc785\ub2c8\ub2e4. uclk_en\ub9c8\ub2e4 state\uac00 \ub118\uc5b4\uac00\ub294 \uac83\uc744 \ud655\uc778\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"has-text-align-center\">0x0(IDLE) -&gt; 0x1(START) -&gt; 0x2(DATA) -&gt; 0x5(TRANSFINISH)<\/p>\n\n\n\n<p>DATA state\uc77c \ub54c data\uac00 1-bit \uc529 shift \ub418\uc5b4 r_shift\uc5d0 \uc800\uc7a5\ub418\uace0 \uadf8\uc5d0 \ub530\ub77c tx signal\uc774 \ubcc0\ud558\ub294 \uac83\uc744 \ud655\uc778\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4. \ub9c8\uc9c0\ub9c9\uc73c\ub85c transfer\uac00 \ub05d\ub098\uba74 complete intr\uac00 \ucf1c\uc9d1\ub2c8\ub2e4.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">\ubb38\uc81c\uc810<\/h4>\n\n\n\n<p>\ubb3c\ub860, \uc774 controller\ub294 \uc644\uc804\ud55c IP\uac00 \uc544\ub2d9\ub2c8\ub2e4. \uc65c\ub0d0\ud558\uba74 1-byte \uc529 \ubcf4\ub0bc \ub54c\ub9c8\ub2e4 intr\ub97c \ub0b4\ubcf4\ub0b4\uae30 \ub54c\ubb38\uc785\ub2c8\ub2e4. \uc77c\ubc18\uc801\uc778 module\uc758 \uacbd\uc6b0, FIFO(First In, First Out) \uba54\ubaa8\ub9ac\uac00 \ub2ec\ub824\uc788\uc5b4\uc11c enable\uc744 \ud558\uba74 \uc0ac\uc6a9\uc790\uac00 \uc77c\ubd80\ub7ec disable \ud558\uc9c0 \uc54a\ub294 \uc774\uc0c1 FIFO \uba54\ubaa8\ub9ac\uac00 \ube44\uc6cc\uc9c8 \ub54c\uae4c\uc9c0 \ub370\uc774\ud130\ub97c \uacc4\uc18d \ubcf4\ub0c5\ub2c8\ub2e4. FIFO\uac00 \ube44\uc6cc\uc9c0\uba74 CPU\uc5d0 intr\ub85c \ub370\uc774\ud130\ub97c \uc694\uccad\ud558\uac70\ub098 DMA(Direct Memory Access)\uc5d0 \ub370\uc774\ud130\ub97c \uc694\uccad\ud558\ub294 \uc2e0\ud638\ub97c \ubcf4\ub0c5\ub2c8\ub2e4.<\/p>\n\n\n<style>.kadence-column712_a80c89-1d > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column712_a80c89-1d > .kt-inside-inner-col,.kadence-column712_a80c89-1d > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column712_a80c89-1d > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column712_a80c89-1d > .kt-inside-inner-col{flex-direction:column;}.kadence-column712_a80c89-1d > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column712_a80c89-1d > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column712_a80c89-1d{position:relative;}@media all and (max-width: 1024px){.kadence-column712_a80c89-1d > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column712_a80c89-1d > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column712_a80c89-1d\"><div class=\"kt-inside-inner-col\">\n<p><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-simulation-settings\/\">[Verilog] Simulation \ud658\uacbd \uc138\ud305 (EDA playground, Icarus verilog)<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-1\/\">[Verilog] UART RTL design 1<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-3\/\">[Verilog] UART RTL design 3<\/a><\/p>\n<\/div><\/div>\n\n\n\n<p>\ucc38\uace0: <a href=\"https:\/\/www.amebaiot.com\/en\/uart\/\" target=\"_blank\" rel=\"noopener\">Realtek UART<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Continuing from the previous post, let's continue with the UART RTL design. Related posts\u2026<\/p>","protected":false},"author":1,"featured_media":741,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_kadence_starter_templates_imported_post":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[39],"tags":[40,99],"class_list":["post-712","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-verilog","tag-verilog","tag-apb-interface"],"_links":{"self":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/712","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/comments?post=712"}],"version-history":[{"count":4,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/712\/revisions"}],"predecessor-version":[{"id":746,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/712\/revisions\/746"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media\/741"}],"wp:attachment":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media?parent=712"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/categories?post=712"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/tags?post=712"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}<!-- This website is optimized by Airlift. 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