{"id":709,"date":"2024-09-22T22:53:43","date_gmt":"2024-09-22T13:53:43","guid":{"rendered":"https:\/\/rtlearner.com\/?p=709"},"modified":"2024-09-28T16:02:10","modified_gmt":"2024-09-28T07:02:10","slug":"verilog-uart-rtl-design-1","status":"publish","type":"post","link":"https:\/\/rtlearner.com\/en\/verilog-uart-rtl-design-1\/","title":{"rendered":"[Verilog] UART RTL design 1"},"content":{"rendered":"\n<p>\uc774\ubc88\uc5d0\ub294 \uac04\ub2e8\ud55c \ud1b5\uc2e0 IP\uc778 UART(Universal Asynchronous Receiver\/Transmitter)\ub97c \uc124\uacc4\ud574\ubcf4\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-table-of-content-nav.kb-table-of-content-id709_854cb0-94 .kb-table-of-content-wrap{padding-top:var(--global-kb-spacing-sm, 1.5rem);padding-right:var(--global-kb-spacing-sm, 1.5rem);padding-bottom:var(--global-kb-spacing-sm, 1.5rem);padding-left:var(--global-kb-spacing-sm, 1.5rem);box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kb-table-of-content-nav.kb-table-of-content-id709_854cb0-94 .kb-table-of-contents-title-wrap{padding-top:0px;padding-right:0px;padding-bottom:0px;padding-left:0px;}.kb-table-of-content-nav.kb-table-of-content-id709_854cb0-94 .kb-table-of-contents-title{font-weight:regular;font-style:normal;}.kb-table-of-content-nav.kb-table-of-content-id709_854cb0-94 .kb-table-of-content-wrap .kb-table-of-content-list{font-weight:regular;font-style:normal;margin-top:var(--global-kb-spacing-sm, 1.5rem);margin-right:0px;margin-bottom:0px;margin-left:0px;}@media all and (max-width: 767px){.kb-table-of-content-nav.kb-table-of-content-id709_854cb0-94 .kb-table-of-contents-title{font-size:var(--global-kb-font-size-md, 1.25rem);}.kb-table-of-content-nav.kb-table-of-content-id709_854cb0-94 .kb-table-of-content-wrap .kb-table-of-content-list{font-size:var(--global-kb-font-size-sm, 0.9rem);}}<\/style>\n\n<style>.kadence-column709_c32196-ac > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column709_c32196-ac > .kt-inside-inner-col,.kadence-column709_c32196-ac > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column709_c32196-ac > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column709_c32196-ac > .kt-inside-inner-col{flex-direction:column;}.kadence-column709_c32196-ac > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column709_c32196-ac > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column709_c32196-ac{position:relative;}@media all and (max-width: 1024px){.kadence-column709_c32196-ac > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column709_c32196-ac > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column709_c32196-ac\"><div class=\"kt-inside-inner-col\">\n<p><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-simulation-settings\/\">[Verilog] Simulation \ud658\uacbd \uc138\ud305 (EDA playground, Icarus verilog)<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-2\/\">[Verilog] UART RTL design 2<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-3\/\">[Verilog] UART RTL design 3<\/a><\/p>\n<\/div><\/div>\n\n\n\n<h2 class=\"wp-block-heading\">UART overview<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">\ud2b9\uc9d5<\/h3>\n\n\n\n<p>UART \ud1b5\uc2e0\uc740 I2C\ub098 SPI\uc640 \ub2ec\ub9ac \ud074\ub7ed(clock)\ub97c \uc0ac\uc6a9\ud558\uc9c0 \uc54a\ub294 \ube44\ub3d9\uae30 \ud1b5\uc2e0\uc785\ub2c8\ub2e4. \ube44\ub3d9\uae30 \ud1b5\uc2e0\uacfc \ub3d9\uae30 \ud1b5\uc2e0\uc740 \uc5b4\ub5a4 \ucc28\uc774\uac00 \uc788\uc744\uae4c\uc694??<\/p>\n\n\n\n<p><strong>\uc7a5\uc810<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>\ud074\ub7ed\uc744 \uc4f0\uc9c0 \uc54a\uae30 \ub54c\ubb38\uc5d0 \ud074\ub7ed \ud540\uc774 \ud544\uc694 \uc5c6\uace0 slave select \ud540\ub3c4 \ud544\uc694 \uc5c6\uc74c, \ub370\uc774\ud130 \uc1a1\uc218\uc2e0\ud558\ub294 2\uac1c\uc758 \ud540\ub9cc \uc0ac\uc6a9<\/li>\n\n\n\n<li>Tx, Rx\uac00 \ub098\ub258\uc5b4\uc838 \uc788\uc5b4\uc11c \uc804\uc774\uc911 \ud1b5\uc2e0 \uc9c0\uc6d0<\/li>\n\n\n\n<li>\uc624\ub7ab\ub3d9\uc548 \uc0ac\uc6a9\ub418\uc5c8\uae30\uc5d0 \ubcf5\uc7a1\ud558\uc9c0 \uc54a\uace0 \uad00\ub828 \ubb38\uc11c\ub3c4 \uc798 \uc815\ub9ac\ub418\uc5b4 \uc788\uc74c, \ub9ce\uc740 \uc7a5\uce58\uac00 \uc9c0\uc6d0<\/li>\n<\/ul>\n\n\n\n<p><strong>\ub2e8\uc810<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>1:1 \ud1b5\uc2e0\uc774\uae30 \ub54c\ubb38\uc5d0 controller\uac00 \ub9ce\uc544\uc9c8\uc218\ub85d wire\uac00 \ub9ce\uc774 \ud544\uc694\ud568<\/li>\n\n\n\n<li>\ud1b5\uc2e0\uc744 \uc704\ud574 \uc804\uc1a1\uc18d\ub3c4(baud rate)\ub97c \uc798 \ub9de\ucdb0\uc918\uc57c \ud558\uace0 \ud2c0\ub9ac\uba74 \ub370\uc774\ud130 \uc190\uc2e4\uc774 \uc77c\uc5b4\ub0a8<\/li>\n<\/ul>\n\n\n<style>.kb-image709_659231-25.kb-image-is-ratio-size, .kb-image709_659231-25 .kb-image-is-ratio-size{max-width:650px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_659231-25.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_659231-25 .kb-image-is-ratio-size{align-self:unset;}.kb-image709_659231-25 figure{max-width:650px;}.kb-image709_659231-25 .image-is-svg, .kb-image709_659231-25 .image-is-svg img{width:100%;}.kb-image709_659231-25 .kb-image-has-overlay:after{opacity:0.3;}.kb-image709_659231-25 img.kb-img, .kb-image709_659231-25 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image709_659231-25.kb-image-is-ratio-size, .kb-image709_659231-25 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image709_659231-25 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image709_659231-25\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/YkPC5\/btso1uWDhcP\/LQiY1lv7Pa7ixsLgyrju4K\/img.png\" alt=\"\uc5f0\uacb0 \ubc29\ubc95\" class=\"kb-img\"\/><figcaption>\uc5f0\uacb0 \ubc29\ubc95<\/figcaption><\/figure><\/div>\n\n\n\n<p>UART control \ubaa8\ub4c8\uc5d0\ub294 Rx\/Tx \ud540\uc774 \uc788\uc5b4\uc11c \ub370\uc774\ud130\uac00 \ub098\uac00\ub294 \uc2e0\ud638\ub294 Tx, \ub370\uc774\ud130\ub97c \uc218\uc2e0\ud558\ub294 \uc2e0\ud638\ub294 Rx\uc5d0 \uc5f0\uacb0\ud558\uba74 \ub429\ub2c8\ub2e4.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Protocol<\/h3>\n\n\n<style>.kb-image709_5676c6-79.kb-image-is-ratio-size, .kb-image709_5676c6-79 .kb-image-is-ratio-size{max-width:650px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_5676c6-79.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_5676c6-79 .kb-image-is-ratio-size{align-self:unset;}.kb-image709_5676c6-79 figure{max-width:650px;}.kb-image709_5676c6-79 .image-is-svg, .kb-image709_5676c6-79 .image-is-svg img{width:100%;}.kb-image709_5676c6-79 .kb-image-has-overlay:after{opacity:0.3;}.kb-image709_5676c6-79 img.kb-img, .kb-image709_5676c6-79 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image709_5676c6-79.kb-image-is-ratio-size, .kb-image709_5676c6-79 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image709_5676c6-79 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image709_5676c6-79\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/ba1oAP\/btsoTnSDn4a\/wvshPBGwD6tScR84vhx00k\/img.png\" alt=\"UART Protocol\" class=\"kb-img\"\/><figcaption>Protocol<\/figcaption><\/figure><\/div>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Baud rate<\/strong><\/li>\n<\/ul>\n\n\n\n<p>UART \ud1b5\uc2e0\uc740 \ube44\ub3d9\uae30 \ubc29\uc2dd\uc758 \uc804\uc774\uc911 \ud1b5\uc2e0\uc73c\ub85c \ub3d9\uae30 \uc2e0\ud638\uc778 \ud074\ub7ed\uc744 \uc0ac\uc6a9\ud558\uc9c0 \uc54a\uae30 \ub54c\ubb38\uc5d0 \ub370\uc774\ud130 \uc1a1\/\uc218\uc2e0 \uc804\uc5d0 \ub370\uc774\ud130 \uc804\uc1a1 \uc18d\ub3c4(baud rate)\ub97c \uc815\ud574\uc57c \ud569\ub2c8\ub2e4. \ub9ce\uc774 \uc0ac\uc6a9\ud558\ub294 baud rate\ub294 38400\uc778\ub370\uc694, \uc774\ub294 38.4 Kbps\ub97c \uc758\ubbf8\ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Start bit<\/strong><\/li>\n<\/ul>\n\n\n\n<p>Baud rate\ub97c \uc815\ud588\uc9c0\ub9cc, \ub370\uc774\ud130\ub97c \uc8fc\uace0\ubc1b\ub294 \ub450 \ubaa8\ub4c8\uc740 \ud1b5\uc2e0\uc758 \uc2dc\uc791\uc744 \uc5b4\ub5bb\uac8c \uc54c \uc218 \uc788\uc744\uae4c\uc694?? UART \ud1b5\uc2e0\uc5d0\ub294 Start bit\uac00 \uc874\uc7ac\ud569\ub2c8\ub2e4. \ud1b5\uc2e0\ud558\uae30 \uc804\uc5d0\ub294 High \uc0c1\ud0dc\ub97c \uc720\uc9c0\ud558\ub2e4\uac00 \ud1b5\uc2e0\uc774 \uc2dc\uc791\ub420 \ub54c, Low\ub85c \ub0b4\ub824\uc8fc\uba74 \ub370\uc774\ud130\ub97c \ubc1b\ub294 \ucabd\uc5d0\uc11c \ud1b5\uc2e0\uc774 \uc2dc\uc791\ub428\uc744 \uc54c \uc218 \uc788\uac8c \ub429\ub2c8\ub2e4.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Stop bit<\/strong><\/li>\n<\/ul>\n\n\n\n<p>8-bit\uc758 \ub370\uc774\ud130\ub97c \uc8fc\uace0\ubc1b\uc740 \ub4a4 High \uc0c1\ud0dc\ub97c \uc720\uc9c0\ud558\uba74 \ud1b5\uc2e0\uc774 \ub05d\ub0ac\ub2e4\ub294 \uac83\uc744 \uc758\ubbf8\ud569\ub2c8\ub2e4. \uc774\ub294 Stop bit\ub77c\uace0 \ud558\ub294\ub370 1~2-bit\ub85c \uc124\uc815\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Parity bit<\/strong><\/li>\n<\/ul>\n\n\n<style>.kb-image709_6c0d30-b2.kb-image-is-ratio-size, .kb-image709_6c0d30-b2 .kb-image-is-ratio-size{max-width:600px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_6c0d30-b2.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_6c0d30-b2 .kb-image-is-ratio-size{align-self:unset;}.kb-image709_6c0d30-b2 figure{max-width:600px;}.kb-image709_6c0d30-b2 .image-is-svg, .kb-image709_6c0d30-b2 .image-is-svg img{width:100%;}.kb-image709_6c0d30-b2 .kb-image-has-overlay:after{opacity:0.3;}.kb-image709_6c0d30-b2 img.kb-img, .kb-image709_6c0d30-b2 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image709_6c0d30-b2.kb-image-is-ratio-size, .kb-image709_6c0d30-b2 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image709_6c0d30-b2 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image709_6c0d30-b2\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/IUng3\/btso217PuXf\/fssLPwXgysDT97f75bLgKK\/img.png\" alt=\"Tera term setting\" class=\"kb-img\"\/><figcaption>Tera term setting<\/figcaption><\/figure><\/div>\n\n\n\n<p>\uc704\uc758 \uc0ac\uc9c4\uc740 PC\uc640 \uc720\uc800\uac00 \uc2dc\ub9ac\uc5bc \ud1b5\uc2e0\uc744 \ud560 \uc218 \uc788\uac8c \ub3c4\uc640\uc8fc\ub294 Tera term\uc774\ub77c\ub294 \ud504\ub85c\uadf8\ub7a8\uc785\ub2c8\ub2e4. \ud1b5\uc2e0\ud558\uae30 \uc804\uc5d0 \uc704\uc640 \uac19\uc740 \uc124\uc815\uc744 \ud558\uac8c \ub418\ub294\ub370\uc694, baud rate\ub294 38400, 1 \ud328\ud0b7\uc740 8 -bit, 1 stop bit\ub85c \uc124\uc815\ud588\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<p>\uadf8\ub9ac\uace0 parity bit\ub3c4 \uc124\uc815\ud574\uc57c \ud569\ub2c8\ub2e4. Parity bit\ub294 \uc720\uc800\uac00 \uc635\uc158\uc73c\ub85c \uc124\uc815\ud558\ub294 \ube44\ud2b8\uc785\ub2c8\ub2e4, \uc548 \uc4f8 \uc218\ub3c4 \uc788\uace0 \uc4f8 \uc218\ub3c4 \uc788\ub294 \uac70\uc8e0. \uc5ed\ud560\uc740 \ud1b5\uc2e0 \uc911 \uc624\ub958\uac00 \uc788\ub294\uc9c0 \uac80\uc0ac\ud558\ub294 \uac83\uc785\ub2c8\ub2e4. \uadf8\ub807\ub2e4\uba74 \uc65c \uc624\ub958\uac00 \ubc1c\uc0dd\ud558\ub294 \uac78\uae4c\uc694??<\/p>\n\n\n\n<p>SoC\uc5d0\uc11c \uc0ac\uc6a9\ub418\ub294 controller\uc758 \uacbd\uc6b0 \ub0b4\ubd80 \ub808\uc9c0\uc2a4\ud130 \uc138\ud305\uc744 \ud1b5\ud574 baud rate\ub97c \uc124\uc815\ud558\uac8c \ub429\ub2c8\ub2e4.<\/p>\n\n\n<style>.kb-image709_45d1a2-64.kb-image-is-ratio-size, .kb-image709_45d1a2-64 .kb-image-is-ratio-size{max-width:300px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_45d1a2-64.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_45d1a2-64 .kb-image-is-ratio-size{align-self:unset;}.kb-image709_45d1a2-64 figure{max-width:300px;}.kb-image709_45d1a2-64 .image-is-svg, .kb-image709_45d1a2-64 .image-is-svg img{width:100%;}.kb-image709_45d1a2-64 .kb-image-has-overlay:after{opacity:0.3;}.kb-image709_45d1a2-64 img.kb-img, .kb-image709_45d1a2-64 .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image709_45d1a2-64.kb-image-is-ratio-size, .kb-image709_45d1a2-64 .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image709_45d1a2-64 figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image709_45d1a2-64\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/xi6oK\/btsJd3sAXwC\/fRzVJif1tcYYAn1WntQNiK\/img.png\" alt=\"Baud rate \uc124\uc815 \uc608\uc2dc\" class=\"kb-img\"\/><figcaption>Baud rate \uc124\uc815 \uc608\uc2dc<\/figcaption><\/figure><\/div>\n\n\n\n<p>\uc774 UART controller \ubaa8\ub4c8\uc758 \uc0ac\uc6a9\ub418\ub294 \ud074\ub7ed\uc774 10MHz\uc774\uace0 \uc6d0\ud558\ub294 baud rate\ub294 38400\uc785\ub2c8\ub2e4. Controller\uc758 \uc0ac\uc6a9\ub418\ub294 \ud074\ub7ed\uc758 \uc8fc\ud30c\uc218\ub97c \uc6d0\ud558\ub294 baud rate\ub85c \ub098\ub220 register \uc138\ud305 \uac12\uc744 \uc815\ud569\ub2c8\ub2e4. \uacc4\uc0b0 \uacb0\uacfc\ub97c \ubc18\uc62c\ub9bc\ud574\uc11c \ubaa8\ub4c8\uc5d0 \uc785\ub825\ud558\ub294\ub370 \uc5ec\uae30\uc11c&nbsp;<strong>\uc5b4\uca54 \uc218 \uc5c6\uc774 \uc624\ucc28\uac00 \ubc1c\uc0dd<\/strong>\ud558\uac8c \ub429\ub2c8\ub2e4. \uc774\uc5d0 \ub530\ub77c \ud1b5\uc2e0 \uc911 \uc624\ub958\uac00 \ubc1c\uc0dd\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<p>\uc815\ub9ac\ud558\uc790\uba74 UART\ub294 \ud074\ub7ed\uc744 \uc0ac\uc6a9\ud558\uc9c0 \uc54a\ub294 \ube44\ub3d9\uae30\ud1b5\uc2e0\uc774\uc5b4\uc11c \ud074\ub7ed \ud540\uc774 \ud544\uc694\ud558\uc9c0 \uc54a\uc9c0\ub9cc, \uc624\ucc28\uac00 \ubc1c\uc0dd\ud560 \uc218 \uc788\uc5b4\uc11c \uc720\uc800\uac00 parity bit\ub97c optional \ud558\uac8c \uc124\uc815\ud574\uc57c \ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Specification<\/h2>\n\n\n\n<p>\uba3c\uc800 \ubd84\uba85\ud788 \ud560 \uac83\uc740, \uc81c\uac00 \uc124\uacc4\ud558\ub294 UART\ub294 \uc2e4\uc81c \uc0ac\uc6a9\ud558\ub294 IP\uc640\ub294 \ucc28\uc774\uc810\uc774 \uc788\uc2b5\ub2c8\ub2e4. \uc774\uc5d0 \ub300\ud574\uc11c\ub294 \ucc28\uadfc\ucc28\uadfc <a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-2\">\uc124\uba85<\/a>\ud558\ub3c4\ub85d \ud558\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Block diagram<\/h3>\n\n\n<style>.kb-image709_7fbd48-ab.kb-image-is-ratio-size, .kb-image709_7fbd48-ab .kb-image-is-ratio-size{max-width:650px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_7fbd48-ab.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image709_7fbd48-ab .kb-image-is-ratio-size{align-self:unset;}.kb-image709_7fbd48-ab figure{max-width:650px;}.kb-image709_7fbd48-ab .image-is-svg, .kb-image709_7fbd48-ab .image-is-svg img{width:100%;}.kb-image709_7fbd48-ab .kb-image-has-overlay:after{opacity:0.3;}.kb-image709_7fbd48-ab img.kb-img, .kb-image709_7fbd48-ab .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image709_7fbd48-ab.kb-image-is-ratio-size, .kb-image709_7fbd48-ab .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image709_7fbd48-ab figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image709_7fbd48-ab\"><figure class=\"aligncenter size-large\"><img data-dominant-color=\"adc4cf\" data-has-transparency=\"false\" style=\"--dominant-color: #adc4cf;\" loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"606\" src=\"https:\/\/rtlearner.com\/wp-content\/uploads\/2024\/08\/\uadf8\ub9bc1-8-1024x606.jpg\" alt=\"\uae00 \uc124\uba85 \uc774\ubbf8\uc9c0, UART block diagram\" class=\"kb-img wp-image-710 not-transparent\" srcset=\"https:\/\/rtlearner.com\/wp-content\/uploads\/2024\/08\/\uadf8\ub9bc1-8-1024x606.jpg 1024w, https:\/\/rtlearner.com\/wp-content\/uploads\/2024\/08\/\uadf8\ub9bc1-8-300x178.jpg 300w, https:\/\/rtlearner.com\/wp-content\/uploads\/2024\/08\/\uadf8\ub9bc1-8-768x454.jpg 768w, https:\/\/rtlearner.com\/wp-content\/uploads\/2024\/08\/\uadf8\ub9bc1-8.jpg 1200w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><figcaption>Block diagram<\/figcaption><\/figure><\/div>\n\n\n\n<p>APB interface\uac00 \uc788\uace0 Tx\/Rx controller\uc5d0 CLK gen(clock generator)\uac00 \ubd99\uc5b4\uc788\uc2b5\ub2c8\ub2e4. CLK gen\uc5d0\uc11c baud rate\ub97c \uc124\uc815\ud574 \uc90d\ub2c8\ub2e4.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Register map<\/h3>\n\n\n\n<p>Register map\uc740 \ub2e4\uc74c\uacfc \uac19\uc774 \uc124\uc815\ud588\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>CTRL register (address: 0x0)<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-table is-style-stripes\"><table><thead><tr><th>Signal name<\/th><th class=\"has-text-align-center\" data-align=\"center\">R\/W<\/th><th class=\"has-text-align-center\" data-align=\"center\">Default value<\/th><th class=\"has-text-align-center\" data-align=\"center\">Bit<\/th><\/tr><\/thead><tbody><tr><td>Reserved<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">31:21<\/td><\/tr><tr><td>Pre_scale<\/td><td class=\"has-text-align-center\" data-align=\"center\">RW<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">20:18<\/td><\/tr><tr><td>Bit_mult<\/td><td class=\"has-text-align-center\" data-align=\"center\">RW<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">17:13<\/td><\/tr><tr><td>Bit_div<\/td><td class=\"has-text-align-center\" data-align=\"center\">RW<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">12:4<\/td><\/tr><tr><td>Reserved<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">3<\/td><\/tr><tr><td>Two_stop_en<\/td><td class=\"has-text-align-center\" data-align=\"center\">RW<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">2<\/td><\/tr><tr><td>Parity_en<\/td><td class=\"has-text-align-center\" data-align=\"center\">RW<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">1<\/td><\/tr><tr><td>Enable<\/td><td class=\"has-text-align-center\" data-align=\"center\">RW<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">0<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">CTRL register<\/figcaption><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Status register (address: 0x4)<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-table is-style-stripes\"><table><thead><tr><th>Signal name<\/th><th class=\"has-text-align-center\" data-align=\"center\">R\/W<\/th><th class=\"has-text-align-center\" data-align=\"center\">Default value<\/th><th class=\"has-text-align-center\" data-align=\"center\">Bit<\/th><\/tr><\/thead><tbody><tr><td>Reserved<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">31:2<\/td><\/tr><tr><td>Rx_complete<\/td><td class=\"has-text-align-center\" data-align=\"center\">W<sub>1<\/sub>C<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">1<\/td><\/tr><tr><td>Tx_complete<\/td><td class=\"has-text-align-center\" data-align=\"center\">W<sub>1<\/sub>C<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">0<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Status register<\/figcaption><\/figure>\n\n\n\n<p>\uc0ac\uc2e4, status\uc5d0 parity error\ub97c \ucd94\uac00\ud574\uc57c \ud569\ub2c8\ub2e4. Parity\uac00 \uc788\ub294 UART \ud1b5\uc2e0\uc77c \ub54c, rx controller\uc5d0\uc11c parity check\ub97c \ud558\uace0 \uc218\uc2e0\ub41c parity\uc640 \uacc4\uc0b0\ub41c parity\uac00 \uc77c\uce58\ud558\uc9c0 \uc54a\uc73c\uba74 error\ub97c \ubc1c\uc0dd\uc2dc\ud0a4\uace0 CPU\uc5d0 \uc774\ub97c \uc54c\ub824\uc57c \ud569\ub2c8\ub2e4. \uadfc\ub370 \uadc0\ucc2e\uc544\uc11c \ube90\uc2b5\ub2c8\ub2e4;;;<\/p>\n\n\n\n<p>\uc9c1\uc811 rx controller\uc5d0 parity check \uae30\ub2a5\uc744 \ub123\uc5b4\ubcf4\ub294 \uac83\ub3c4 \uc88b\uaca0\ub124\uc694!!<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Tx data register (address: 0x8)<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-table is-style-stripes\"><table><thead><tr><th>Signal name<\/th><th class=\"has-text-align-center\" data-align=\"center\">R\/W<\/th><th class=\"has-text-align-center\" data-align=\"center\">Default value<\/th><th class=\"has-text-align-center\" data-align=\"center\">Bit<\/th><\/tr><\/thead><tbody><tr><td>Reserved<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">31:8<\/td><\/tr><tr><td>Tx_data<\/td><td class=\"has-text-align-center\" data-align=\"center\">RW<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">7:0<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Tx data register<\/figcaption><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Rx data register (address: 0xC)<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-table is-style-stripes\"><table><thead><tr><th>Signal name<\/th><th class=\"has-text-align-center\" data-align=\"center\">R\/W<\/th><th class=\"has-text-align-center\" data-align=\"center\">Default value<\/th><th class=\"has-text-align-center\" data-align=\"center\">Bit<\/th><\/tr><\/thead><tbody><tr><td>Reserved<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">&#8211;<\/td><td class=\"has-text-align-center\" data-align=\"center\">31:8<\/td><\/tr><tr><td>Rx_data<\/td><td class=\"has-text-align-center\" data-align=\"center\">RO<\/td><td class=\"has-text-align-center\" data-align=\"center\">0x0<\/td><td class=\"has-text-align-center\" data-align=\"center\">7:0<\/td><\/tr><\/tbody><\/table><figcaption class=\"wp-element-caption\">Rx data register<\/figcaption><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\">UART RTL design<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">APB interface RTL design<\/h3>\n\n\n\n<p>\uc704\uc758 register map\uc744 \uae30\ubc18\uc73c\ub85c APB interface\ub97c \uc124\uacc4\ud574 \ubd05\uc2dc\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" data-code=\"module uart_apb (\n     \/\/APB Interface\n     input  wire        pclk\n    ,input  wire        presetn\n    ,input  wire        penable\n    ,input  wire        psel\n    ,input  wire [ 5:2] paddr\n    ,input  wire        pwrite\n    ,input  wire [31:0] pwdata\n    ,output wire [31:0] prdata\n \n     \/\/Baud rate\n    ,output wire [ 8:0] bit_div\n    ,output wire [ 2:0] pre_scale\n    ,output wire [ 4:0] bit_mult\n\n     \/\/Register Interface\n    ,input  wire        tx_complete\n    ,input  wire        rx_complete\n    ,output wire        tx_clr\n    ,output wire        rx_clr\n    ,output wire        uart_en\n    ,output wire        parity_en\n    ,output wire        stop_en\n    ,input  wire [ 7:0] uart_rxdata\n    ,output wire [ 7:0] uart_txdata\n);\n\n    \/\/===================================================================\n    \/\/ Local Parameters\n    \/\/===================================================================\n    localparam INVALID_DATA = 32'hDEAD_DEAD;\n    \n    \/\/===================================================================\n    \/\/ Internal Signals\n    \/\/===================================================================\n    wire        we = psel &amp; ~penable &amp;   pwrite;\n    wire        re = psel &amp; ~penable &amp;  ~pwrite;\n    reg  [31:0] RD ;\n      \n    \/\/===================================================================\n    \/\/ Address Decode \n    \/\/===================================================================\n    wire        ctrl    = (paddr[ 5:2] == 4'h0);\n    wire        st      = (paddr[ 5:2] == 4'h1);\n    wire        tx_data = (paddr[ 5:2] == 4'h2);\n    wire        rx_data = (paddr[ 5:2] == 4'h3);\n     \n    \/\/===================================================================\n    \/\/ Write Enable\n    \/\/===================================================================\n    wire        we_ctrl = we &amp; ctrl;\n    wire        we_data = we &amp; tx_data;\n    wire        we_st   = we &amp; st;\n    \n    \/\/===================================================================\n    \/\/ Register Files \n    \/\/===================================================================\n    reg         r_enable;\n    always @(posedge pclk or negedge presetn) begin\n        if(!presetn)      r_enable &lt;= 1'b0;\n        else if (tx_clr)  r_enable &lt;= 1'b0;\n        else if (we_ctrl) r_enable &lt;= pwdata[0];\n        else              r_enable &lt;= r_enable;\n    end\n\n    reg         r_parity;\n    always @(posedge pclk or negedge presetn) begin\n        if(!presetn)      r_parity &lt;= 1'b0;\n        else if (we_ctrl) r_parity &lt;= pwdata[1];\n        else              r_parity &lt;= r_parity;\n    end\n\n    reg         r_stop;\n    always @(posedge pclk or negedge presetn) begin\n        if(!presetn)      r_stop &lt;= 1'b0;\n        else if (we_ctrl) r_stop &lt;= pwdata[2];\n        else              r_stop &lt;= r_stop;\n    end\n\n    reg  [16:0] r_bitcfg;\n    always @(posedge pclk or negedge presetn) begin\n        if (!presetn)     r_bitcfg &lt;= 17'h0;\n        else if (we_ctrl) r_bitcfg &lt;= pwdata[21:4];\n        else              r_bitcfg &lt;= r_bitcfg;\n    end\n\n    reg  [ 7:0] r_txdata;\n    always @(posedge pclk or negedge presetn) begin\n        if(!presetn)      r_txdata &lt;= 8'h0;\n        else if (we_data) r_txdata &lt;= pwdata[7:0];\n        else              r_txdata &lt;= r_txdata;\n    end\n \n    \/\/===================================================================\n    \/\/ Read Decode\n    \/\/===================================================================\n    always @(*) begin\n        if(re) begin\n            case (paddr[5:2])\n                4'h0 : RD = {11'h0, r_bitcfg, 1'b0, r_stop, r_parity, r_enable};\n                4'h1 : RD = {30'b0, rx_complete, tx_complete};\n                4'h2 : RD = {24'b0, r_txdata};\n                4'h3 : RD = {24'b0, uart_rxdata};\n                default : RD = INVALID_DATA;\n            endcase\n        end\n        else RD = INVALID_DATA;\n    end\n    \n    assign  prdata = RD;\n    \n    \/\/===================================================================\n    \/\/ Output Assign\n    \/\/===================================================================\n    assign bit_div     = r_bitcfg[ 8: 0];\n    assign bit_mult    = r_bitcfg[13: 9];\n    assign pre_scale   = r_bitcfg[16:14];\n\n    assign parity_en   = r_parity;\n    assign stop_en     = r_stop;\n    assign uart_en     = r_enable;\n    assign uart_txdata = r_txdata;\n\n    assign tx_clr      = we_st &amp; pwdata[0];\n    assign rx_clr      = we_st &amp; pwdata[1];\n\nendmodule\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> uart_apb (<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">     <\/span><span style=\"color: #616E88\">\/\/APB Interface<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pclk<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        presetn<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        penable<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        psel<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">] paddr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        pwrite<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [<\/span><span style=\"color: #B48EAD\">31<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] pwdata<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [<\/span><span style=\"color: #B48EAD\">31<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] prdata<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\"> <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">     <\/span><span style=\"color: #616E88\">\/\/Baud rate<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">8<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] bit_div<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] pre_scale<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">4<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] bit_mult<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">     <\/span><span style=\"color: #616E88\">\/\/Register Interface<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_complete<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_complete<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_clr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_clr<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        uart_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        parity_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        stop_en<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">input<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] uart_rxdata<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    ,<\/span><span style=\"color: #81A1C1\">output<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\"> [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] uart_txdata<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Local Parameters<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">localparam<\/span><span style=\"color: #D8DEE9FF\"> INVALID_DATA <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">32&#39;hDEAD_DEAD<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Internal Signals<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        we <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> psel <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">~<\/span><span style=\"color: #D8DEE9FF\">penable <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\">   pwrite;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        re <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> psel <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">~<\/span><span style=\"color: #D8DEE9FF\">penable <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\">  <\/span><span style=\"color: #81A1C1\">~<\/span><span style=\"color: #D8DEE9FF\">pwrite;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [<\/span><span style=\"color: #B48EAD\">31<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] RD ;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">      <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Address Decode <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        ctrl    <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (paddr[ <\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">] <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">4&#39;h0<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        st      <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (paddr[ <\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">] <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">4&#39;h1<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        tx_data <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (paddr[ <\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">] <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">4&#39;h2<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        rx_data <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> (paddr[ <\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">] <\/span><span style=\"color: #81A1C1\">==<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">4&#39;h3<\/span><span style=\"color: #D8DEE9FF\">);<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">     <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Write Enable<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        we_ctrl <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> we <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> ctrl;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        we_data <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> we <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> tx_data;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">wire<\/span><span style=\"color: #D8DEE9FF\">        we_st   <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> we <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> st;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Register Files <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_enable;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\">(<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)      r_enable <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (tx_clr)  r_enable <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (we_ctrl) r_enable <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> pwdata[<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">              r_enable <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_enable;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_parity;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\">(<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)      r_parity <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (we_ctrl) r_parity <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> pwdata[<\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">              r_parity <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_parity;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">         r_stop;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\">(<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)      r_stop <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (we_ctrl) r_stop <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> pwdata[<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">              r_stop <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_stop;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [<\/span><span style=\"color: #B48EAD\">16<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_bitcfg;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)     r_bitcfg <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">17&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (we_ctrl) r_bitcfg <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> pwdata[<\/span><span style=\"color: #B48EAD\">21<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">4<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">              r_bitcfg <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_bitcfg;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">reg<\/span><span style=\"color: #D8DEE9FF\">  [ <\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">] r_txdata;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">posedge<\/span><span style=\"color: #D8DEE9FF\"> pclk <\/span><span style=\"color: #81A1C1\">or<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">negedge<\/span><span style=\"color: #D8DEE9FF\"> presetn) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\">(<\/span><span style=\"color: #81A1C1\">!<\/span><span style=\"color: #D8DEE9FF\">presetn)      r_txdata <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #B48EAD\">8&#39;h0<\/span><span style=\"color: #D8DEE9FF\">;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\"> (we_data) r_txdata <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> pwdata[<\/span><span style=\"color: #B48EAD\">7<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\">              r_txdata <\/span><span style=\"color: #81A1C1\">&lt;=<\/span><span style=\"color: #D8DEE9FF\"> r_txdata;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\"> <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Read Decode<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">always<\/span><span style=\"color: #D8DEE9FF\"> @(<\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\">) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">if<\/span><span style=\"color: #D8DEE9FF\">(re) <\/span><span style=\"color: #81A1C1\">begin<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">case<\/span><span style=\"color: #D8DEE9FF\"> (paddr[<\/span><span style=\"color: #B48EAD\">5<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">2<\/span><span style=\"color: #D8DEE9FF\">])<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">4&#39;h0<\/span><span style=\"color: #D8DEE9FF\"> : RD <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> {<\/span><span style=\"color: #B48EAD\">11&#39;h0<\/span><span style=\"color: #D8DEE9FF\">, r_bitcfg, <\/span><span style=\"color: #B48EAD\">1&#39;b0<\/span><span style=\"color: #D8DEE9FF\">, r_stop, r_parity, r_enable};<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">4&#39;h1<\/span><span style=\"color: #D8DEE9FF\"> : RD <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> {<\/span><span style=\"color: #B48EAD\">30&#39;b0<\/span><span style=\"color: #D8DEE9FF\">, rx_complete, tx_complete};<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">4&#39;h2<\/span><span style=\"color: #D8DEE9FF\"> : RD <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> {<\/span><span style=\"color: #B48EAD\">24&#39;b0<\/span><span style=\"color: #D8DEE9FF\">, r_txdata};<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #B48EAD\">4&#39;h3<\/span><span style=\"color: #D8DEE9FF\"> : RD <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> {<\/span><span style=\"color: #B48EAD\">24&#39;b0<\/span><span style=\"color: #D8DEE9FF\">, uart_rxdata};<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">                <\/span><span style=\"color: #81A1C1\">default<\/span><span style=\"color: #D8DEE9FF\"> : RD <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> INVALID_DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">            <\/span><span style=\"color: #81A1C1\">endcase<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">        <\/span><span style=\"color: #81A1C1\">else<\/span><span style=\"color: #D8DEE9FF\"> RD <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> INVALID_DATA;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">end<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\">  prdata <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> RD;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/ Output Assign<\/span><\/span>\n<span class=\"line\"><span style=\"color: #ECEFF4\">    <\/span><span style=\"color: #616E88\">\/\/===================================================================<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> bit_div     <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_bitcfg[ <\/span><span style=\"color: #B48EAD\">8<\/span><span style=\"color: #D8DEE9FF\">: <\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> bit_mult    <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_bitcfg[<\/span><span style=\"color: #B48EAD\">13<\/span><span style=\"color: #D8DEE9FF\">: <\/span><span style=\"color: #B48EAD\">9<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> pre_scale   <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_bitcfg[<\/span><span style=\"color: #B48EAD\">16<\/span><span style=\"color: #ECEFF4\">:<\/span><span style=\"color: #B48EAD\">14<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> parity_en   <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_parity;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> stop_en     <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_stop;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> uart_en     <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_enable;<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> uart_txdata <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> r_txdata;<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> tx_clr      <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> we_st <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> pwdata[<\/span><span style=\"color: #B48EAD\">0<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">    <\/span><span style=\"color: #81A1C1\">assign<\/span><span style=\"color: #D8DEE9FF\"> rx_clr      <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> we_st <\/span><span style=\"color: #81A1C1\">&amp;<\/span><span style=\"color: #D8DEE9FF\"> pwdata[<\/span><span style=\"color: #B48EAD\">1<\/span><span style=\"color: #D8DEE9FF\">];<\/span><\/span>\n<span class=\"line\"><\/span>\n<span class=\"line\"><span style=\"color: #81A1C1\">endmodule<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\ub2e4\uc74c \uae00\uc5d0\uc11c \uc774\uc5b4\uc11c \uc124\uba85\ud558\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n<style>.kadence-column709_44df16-73 > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column709_44df16-73 > .kt-inside-inner-col,.kadence-column709_44df16-73 > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column709_44df16-73 > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column709_44df16-73 > .kt-inside-inner-col{flex-direction:column;}.kadence-column709_44df16-73 > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column709_44df16-73 > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column709_44df16-73{position:relative;}@media all and (max-width: 1024px){.kadence-column709_44df16-73 > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column709_44df16-73 > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column709_44df16-73\"><div class=\"kt-inside-inner-col\">\n<p><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-simulation-settings\/\">[Verilog] Simulation \ud658\uacbd \uc138\ud305 (EDA playground, Icarus verilog)<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-2\/\">[Verilog] UART RTL design 2<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/verilog-uart-rtl-design-3\/\">[Verilog] UART RTL design 3<\/a><\/p>\n<\/div><\/div>\n\n\n\n<p>\ucc38\uace0: <a href=\"https:\/\/www.amebaiot.com\/en\/uart\/\" target=\"_blank\" rel=\"noopener\">Realtek UART<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This time, we'll design a simple communication IP, a Universal Asynchronous Receiver\/Transmitter (UART). Related article\u2026<\/p>","protected":false},"author":1,"featured_media":710,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_kadence_starter_templates_imported_post":false,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[39],"tags":[40,99],"class_list":["post-709","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-verilog","tag-verilog","tag-apb-interface"],"_links":{"self":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/709","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/comments?post=709"}],"version-history":[{"count":6,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/709\/revisions"}],"predecessor-version":[{"id":871,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/709\/revisions\/871"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media\/710"}],"wp:attachment":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media?parent=709"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/categories?post=709"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/tags?post=709"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}<!-- This website is optimized by Airlift. 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