{"id":7,"date":"2024-06-26T17:00:56","date_gmt":"2024-06-26T08:00:56","guid":{"rendered":"https:\/\/theme.wplaybook.com\/?p=1"},"modified":"2025-12-29T15:42:13","modified_gmt":"2025-12-29T06:42:13","slug":"fpga-xdc-setting","status":"publish","type":"post","link":"https:\/\/rtlearner.com\/en\/fpga-xdc-setting\/","title":{"rendered":"[FPGA] xdc \uc124\uc815 \ubc29\ubc95 \ubc0f \uae30\ud0c0 \uc5d0\ub7ec \ud574\uacb0"},"content":{"rendered":"\n<p class=\"has-medium-font-size\">RTL \uc124\uacc4\ub97c \ud558\uace0 \ubcf4\ub4dc \uc0c1\uc5d0\uc11c \uac80\uc99d\uc744 \ud558\uae30 \uc704\ud574\uc11c\ub294 bit \ud30c\uc77c\uc744 \uc0dd\uc131\ud574\uc57c\ud569\ub2c8\ub2e4. \uc774\ub97c \uc704\ud574\uc11c\ub294 xdc \ud30c\uc77c\uc744 \ub9cc\ub4e4\uc5b4\uc57c \ud558\ub294\ub370, \uc774 \ud30c\uc77c\uc740 \ubcf4\ub4dc\uc758 \ub3d9\uc791\uc744 \ucd5c\uc801\ud654\ud558\uace0 \uc81c\ub300\ub85c \ub3d9\uc791\uc2dc\ud0a4\uae30 \uc704\ud55c constraint \ud30c\uc77c\uc774\uae30 \ub54c\ubb38\uc5d0 \uac80\uc99d\uc5d0 \ud544\uc218\uc801\uc785\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"has-medium-font-size\">\uc774 \uae00\uc5d0\uc11c\ub294 \ubcf4\ub4dc test\ub97c \uc704\ud55c constraint\ub97c \uc791\uc131\ud558\ub294 \ubc29\ubc95\uc5d0 \ub300\ud574 \uc54c\uc544\ubcf4\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-9d6595d7 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:100%\">\n<div class=\"wp-block-group is-vertical is-layout-flex wp-container-core-group-is-layout-8cf370e7 wp-block-group-is-layout-flex\"><style>.kb-table-of-content-nav.kb-table-of-content-id7_e909d8-bc .kb-table-of-content-wrap{padding-top:var(--global-kb-spacing-sm, 1.5rem);padding-right:var(--global-kb-spacing-sm, 1.5rem);padding-bottom:var(--global-kb-spacing-sm, 1.5rem);padding-left:var(--global-kb-spacing-sm, 1.5rem);box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kb-table-of-content-nav.kb-table-of-content-id7_e909d8-bc .kb-table-of-contents-title-wrap{padding-top:0px;padding-right:0px;padding-bottom:0px;padding-left:0px;}.kb-table-of-content-nav.kb-table-of-content-id7_e909d8-bc .kb-table-of-contents-title{font-weight:regular;font-style:normal;}.kb-table-of-content-nav.kb-table-of-content-id7_e909d8-bc .kb-table-of-content-wrap .kb-table-of-content-list{font-weight:regular;font-style:normal;margin-top:var(--global-kb-spacing-sm, 1.5rem);margin-right:0px;margin-bottom:0px;margin-left:0px;}@media all and (max-width: 767px){.kb-table-of-content-nav.kb-table-of-content-id7_e909d8-bc .kb-table-of-contents-title{font-size:var(--global-kb-font-size-md, 1.25rem);}.kb-table-of-content-nav.kb-table-of-content-id7_e909d8-bc .kb-table-of-content-wrap .kb-table-of-content-list{font-size:var(--global-kb-font-size-sm, 0.9rem);}}<\/style><\/div>\n<\/div>\n<\/div>\n\n\n<style>.kadence-column7_06d6c1-2c > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column7_06d6c1-2c > .kt-inside-inner-col,.kadence-column7_06d6c1-2c > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column7_06d6c1-2c > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column7_06d6c1-2c > .kt-inside-inner-col{flex-direction:column;}.kadence-column7_06d6c1-2c > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column7_06d6c1-2c > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column7_06d6c1-2c{position:relative;}@media all and (max-width: 1024px){.kadence-column7_06d6c1-2c > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column7_06d6c1-2c > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column7_06d6c1-2c\"><div class=\"kt-inside-inner-col\">\n<p><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/fpga-ila-setup-guide\/\">ILA \ubaa8\ub4c8 \uc124\uc815 \ubc0f \uc0ac\uc6a9 \uac00\uc774\ub4dc<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/fpga-dcm-setup-guide\/\">DCM \ubaa8\ub4c8 \uc124\uc815 \ubc0f \uc0ac\uc6a9 \uac00\uc774\ub4dc<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/fpga-block-memory-setup-guide\/\">Block memory \ubaa8\ub4c8 \uc124\uc815 \ubc0f \uc0ac\uc6a9 \uac00\uc774\ub4dc<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/vio-setup-guide\/\">VIO \uc0ac\uc6a9 \uac00\uc774\ub4dc, pin test<\/a><\/p>\n<\/div><\/div>\n\n\n\n<h2 class=\"wp-block-heading\">XDC(Xilinx Design Constraint) \uc124\uba85<\/h2>\n\n\n\n<p class=\"has-medium-font-size\">Constraint \ud30c\uc77c\uc740 vivado tool\uc5d0\uc11c \uc0ac\uc6a9\ud558\ub294 design constraint \ud30c\uc77c\ub85c \ubcf4\ub4dc\ub97c \uc0ac\uc6a9\ud55c test\ub97c \uc704\ud574 \uc5ec\ub7ec \uac00\uc9c0 constraint\ub97c \uc124\uc815\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4. \uc774 \ud30c\uc77c\uc5d0\uc11c \uc124\uc815\ud574 \uc8fc\ub294 constraint\uc5d0\ub294 \ub300\ud45c\uc801\uc73c\ub85c clock constraint, \ud540 \uc124\uc815, pull up\/down \uc124\uc815 \ub4f1\uc774 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Clock constraint<\/h3>\n\n\n\n<p class=\"has-theme-palette-3-color has-text-color has-link-color has-medium-font-size wp-elements-5749f3031e03f0ccedb9198ab2273a5c\">Chip\uc744 \uc124\uacc4\ud560 \ub54c input\uc73c\ub85c \ub4e4\uc5b4\uc624\ub294 clock\ub4e4\uc774 \uc788\uc2b5\ub2c8\ub2e4. \ubcf4\ub4dc\uc5d0\ub3c4 \uc624\uc2e4\ub808\uc774\ud130\ub97c \ub2ec\uc544\uc11c clock\uc744 \uc0dd\uc131\ud574\uc8fc\uac70\ub098 \ub514\ubc84\uae45 \uc6a9 JTAG\uc744 \uc5f0\uacb0\ud560 \ub54c \ub4e4\uc5b4\uc624\ub294 clock\uc740 constraint\ub97c \uc124\uc815\ud574\uc918\uc57c \ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"has-theme-palette-3-color has-text-color has-link-color has-small-font-size wp-elements-9a4d7de8da4ccd71de6dcb7af17543ef\"><br>create_clock -period <strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#fe0000\" class=\"has-inline-color\">50.000<\/mark><\/strong> -name <mark style=\"background-color:rgba(0, 0, 0, 0);color:#fe0202\" class=\"has-inline-color\"><strong>clock1<\/strong> <\/mark>-waveform {0.000 <strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#ff0000\" class=\"has-inline-color\">25.000<\/mark><\/strong>} [get_ports <strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#fe0000\" class=\"has-inline-color\">input_port<\/mark><\/strong>]<\/p>\n\n\n\n<p class=\"has-theme-palette-3-color has-text-color has-link-color has-medium-font-size wp-elements-1a4373f21e8244307416d21ae0a1a2b1\"><br><strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#ff0000\" class=\"has-inline-color\">\ube68\uac04\uc0c9 \uae00\uc528<\/mark><\/strong>\uac00 \uc720\uc800\uac00 \uc124\uc815\ud574\uc57c\ud558\ub294 \ubd80\ubd84\uc785\ub2c8\ub2e4. Clock\uc758 \uc8fc\uae30\uc640 \uc774\ub984\uc744 \uc124\uc815\ud574 \uc8fc\uace0 \uc2e4\uc81c RTL \ucf54\ub4dc\uc5d0\uc11c clock\uc774 \ub4e4\uc5b4\uc624\ub294 input port\uc758 \uc774\ub984\uc744 \uc368\ub123\uc5b4\uc8fc\uba74 \ub429\ub2c8\ub2e4. \uadf8\ub7ec\ub2c8\uae4c RTL\ub85c \uc124\uacc4\ud55c chip_top\uc5d0\uc11c <strong>input_port<\/strong> \ud540\uc73c\ub85c \ub4e4\uc5b4\uc624\ub294 clock\uc740 <strong>\uc8fc\uae30\uac00 50ns<\/strong>\uc774\uace0 <strong>clock1<\/strong>\uc774\ub77c\uace0 \uba85\uba85\ud558\ub294 \uac70\uc8e0.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Pin \uc124\uc815(pin \ub9f5\ud551)<\/h3>\n\n\n\n<p class=\"has-medium-font-size\">FPGA \ubcf4\ub4dc\uc5d0\ub294 \uc5ec\ub7ec IO \ud540\uc774 \uc788\uc2b5\ub2c8\ub2e4, \ub2f9\uc5f0\ud788 chip_top\uc758 input, output\ub4e4\uacfc FPGA\uc758 IO\ud540\ub4e4\uc744 \uc5f0\uacb0\ud574\uc918\uc57c\uaca0\uc8e0?? \uadf8\ub7ec\uae30 \uc704\ud574\uc11c\ub294 \uba3c\uc800 \ub0b4\uac00 \uc0ac\uc6a9\ud558\ub294 \ubcf4\ub4dc\uc758 Data sheet\ub97c \ubcf4\uace0 pin map\uc744 \ud30c\uc545\ud574\uc57c \ud569\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"has-medium-font-size\">\uc608\ub97c \ub4e4\uc5b4, RTL top\uc5d0\uc11c GPIO0\ub77c\uace0 \ud558\ub294 inout\uc744 \ubcf4\ub4dc\uc758 A0\ub77c\uace0 \ud558\ub294 \ud540(Data sheet\uc5d0 \ub098\uc640\uc788\uc2b5\ub2c8\ub2e4)\uc5d0 \uc5f0\uacb0\ud558\uace0 \uc2f6\ub2e4\uace0 \ud55c\ub2e4\uba74,<\/p>\n\n\n\n<p class=\"has-small-font-size\">set_property PACKAGE_PIN <strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#ff0000\" class=\"has-inline-color\">A0<\/mark><\/strong> [get_ports <strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#fb0000\" class=\"has-inline-color\">GPIO0<\/mark><\/strong>]<\/p>\n\n\n\n<p class=\"has-medium-font-size\">\ub77c\uace0 \uc791\uc131\ud558\uc2dc\uba74 \ub429\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"has-medium-font-size\">\ub2e4\uc74c\uc73c\ub85c\ub294 \ud574\ub2f9 \ud540\uc758 \uc804\uc555 \uc124\uc815\uc744 \ud558\ub294\ub370\uc694, \ub300\ubd80\ubd84 3.3V\ub098 1.8V\ub97c \uc501\ub2c8\ub2e4.<\/p>\n\n\n\n<p class=\"has-small-font-size\">set_property IOSTANDARD LVCMOS<strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#ff0000\" class=\"has-inline-color\">33<\/mark><\/strong> [get_ports&nbsp;<strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#ff0000\" class=\"has-inline-color\">GPIO0<\/mark><\/strong>]<\/p>\n\n\n\n<p class=\"has-medium-font-size\">3.3V\uc77c \ub54c\ub294 LVCMOS33, 1.8V\uc77c \ub54c\ub294 LVCMOS18\ub85c \uc791\uc131\ud574 \uc8fc\uc2dc\uba74 \ub429\ub2c8\ub2e4~~<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">pull up\/down \uc138\ud305<\/h3>\n\n\n\n<p class=\"has-medium-font-size\">\ub9c8\uc9c0\ub9c9\uc73c\ub85c pull-up, pull-down\uc744 \uc124\uc815\ud574 \uc90d\ub2c8\ub2e4. I2C\ub098 SPI\uac19\uc740 \ud1b5\uc2e0 IP\ub97c \uc4f0\uace0 \uc2f6\uc744 \ub550 \ub2f9\uc5f0\ud788 pull-up\uc73c\ub85c \uc124\uc815\ud574\uc57c\uaca0\uc8e0??<\/p>\n\n\n\n<p class=\"has-small-font-size\">set_property PULLUP <strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#ff0000\" class=\"has-inline-color\">true <\/mark><\/strong>[get_ports&nbsp;<strong><mark style=\"background-color:rgba(0, 0, 0, 0);color:#ff0000\" class=\"has-inline-color\">GPIO0<\/mark><\/strong>]<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">\uae30\ud0c0 \uc5d0\ub7ec \ud574\uacb0<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">DONT TOUCH<\/h3>\n\n\n\n<h4 class=\"wp-block-heading\">\ubb38\uc81c \ubc1c\uc0dd<\/h4>\n\n\n\n<p>System Verilog \ud30c\uc77c\uc744 \ubc1b\uc544\uc11c FPGA \ud569\uc131\uc744 \ub3cc\ub9ac\uace0 test\ub97c \uc9c4\ud589\ud588\uc2b5\ub2c8\ub2e4. \uadf8\ub7f0\ub370 \uc790\uafb8 \uc5d0\ub7ec\uac00 \ubc1c\uc0dd\ud558\ub294\ub370 \uadf8 \uc6d0\uc778\uc774 \ubaa8\ub4c8 \ud558\ub098\uac00 \uc544\uc608 \ube60\uc9c4 \uac83 \uac19\ub354\ub77c\uace0\uc694;; \uadf8\ub798\uc11c source \ubaa9\ub85d\uc744 \ud655\uc778\ud574 \ubd24\ub294\ub370 source\uc5d0\ub294 \uc81c\ub300\ub85c import \ub41c \ubaa8\ub4c8\ub4e4\uc774 Synthesis \ud6c4 Netlist \ubaa9\ub85d\uc5d0 \uc5c6\ub294 \uac83\uc744 \ud655\uc778\ud588\uc2b5\ub2c8\ub2e4. \ubb34\uc2a8 \uc774\uc720\uc778\uc9c0 \ubaa8\ub974\uaca0\uc9c0\ub9cc \ud569\uc131 \uacfc\uc815\uc5d0\uc11c Vivado tool\uc774 \uc544\uc608 \ub0a0\ub824\ubc84\ub9b0 \uac83 \uac19\ub354\ub77c\uace0\uc694;;<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">DONT_TOUCH\ub85c \ud574\uacb0<\/h4>\n\n\n\n<p>Vivado tool\uc774 \ubaa8\ub4c8\uc744 \ub0a0\ub9ac\uc9c0 \ubabb\ud558\uac8c \ucc98\ub9ac\ud558\ub294 \ubc29\ubc95\uc774 \uc788\uc2b5\ub2c8\ub2e4, \ubc14\ub85c DONT_TOUCH\uc778\ub370\uc694, <a href=\"https:\/\/docs.xilinx.com\/r\/en-US\/ug901-vivado-synthesis\/Verilog-Module-Example\" target=\"_blank\" rel=\"noopener\">\ub9c1\ud06c<\/a>\ub85c \uac00\uc2dc\uba74 \uc608\uc81c\ub97c \ud655\uc778\ud574 \ubcf4\uc2e4 \uc218 \uc788\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<div class=\"wp-block-kevinbatdorf-code-block-pro\" data-code-block-pro-font-family=\"Code-Pro-JetBrains-Mono\" style=\"font-size:.875rem;font-family:Code-Pro-JetBrains-Mono,ui-monospace,SFMono-Regular,Menlo,Monaco,Consolas,monospace;line-height:1.25rem;--cbp-tab-width:2;tab-size:var(--cbp-tab-width, 2)\"><span style=\"display:block;padding:16px 0 0 16px;margin-bottom:-1px;width:100%;text-align:left;background-color:#2e3440ff\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"54\" height=\"14\" viewBox=\"0 0 54 14\"><g fill=\"none\" fill-rule=\"evenodd\" transform=\"translate(1 1)\"><circle cx=\"6\" cy=\"6\" r=\"6\" fill=\"#FF5F56\" stroke=\"#E0443E\" stroke-width=\".5\"><\/circle><circle cx=\"26\" cy=\"6\" r=\"6\" fill=\"#FFBD2E\" stroke=\"#DEA123\" stroke-width=\".5\"><\/circle><circle cx=\"46\" cy=\"6\" r=\"6\" fill=\"#27C93F\" stroke=\"#1AAB29\" stroke-width=\".5\"><\/circle><\/g><\/svg><\/span><span role=\"button\" tabindex=\"0\" style=\"color:#d8dee9ff;display:none\" aria-label=\"Copy\" class=\"code-block-pro-copy-button\"><pre class=\"code-block-pro-copy-button-pre\" aria-hidden=\"true\"><textarea class=\"code-block-pro-copy-button-textarea\" tabindex=\"-1\" aria-hidden=\"true\" readonly>(* DONT_TOUCH = \"yes\" *) \/\/DONT_TOUCH\nmodule example_dt_ver\n(clk,\nIn1,\nIn2,\nout1);<\/textarea><\/pre><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" style=\"width:24px;height:24px\" fill=\"none\" viewBox=\"0 0 24 24\" stroke=\"currentColor\" stroke-width=\"2\"><path class=\"with-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2m-6 9l2 2 4-4\"><\/path><path class=\"without-check\" stroke-linecap=\"round\" stroke-linejoin=\"round\" d=\"M9 5H7a2 2 0 00-2 2v12a2 2 0 002 2h10a2 2 0 002-2V7a2 2 0 00-2-2h-2M9 5a2 2 0 002 2h2a2 2 0 002-2M9 5a2 2 0 012-2h2a2 2 0 012 2\"><\/path><\/svg><\/span><pre class=\"shiki nord\" style=\"background-color: #2e3440ff\" tabindex=\"0\"><code><span class=\"line\"><span style=\"color: #D8DEE9FF\">(<\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\"> DONT_TOUCH <\/span><span style=\"color: #81A1C1\">=<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #A3BE8C\">&quot;yes&quot;<\/span><span style=\"color: #D8DEE9FF\"> <\/span><span style=\"color: #81A1C1\">*<\/span><span style=\"color: #D8DEE9FF\">) <\/span><span style=\"color: #616E88\">\/\/DONT_TOUCH<\/span><\/span>\n<span class=\"line\"><span style=\"color: #81A1C1\">module<\/span><span style=\"color: #D8DEE9FF\"> example_dt_ver<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">(clk,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">In1,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">In2,<\/span><\/span>\n<span class=\"line\"><span style=\"color: #D8DEE9FF\">out1);<\/span><\/span><\/code><\/pre><\/div>\n\n\n\n<p>\ubc29\ubc95\uc740 RTL \ucf54\ub4dc \uac00\uc7a5 \uc704\uc5d0 \uc788\ub294 module \uc120\uc5b8 \uc704\uc5d0 (* DONT_TOUCH = &#8220;yes&#8221; *)\ub97c \uc785\ub825\ud558\uc2dc\uba74 \ub429\ub2c8\ub2e4. \uc704\uc758 \ucc98\ub9ac\ub97c \ud574\uc8fc\ub2c8\uae4c Synthesis \ud6c4 \ud569\uc131\ub41c Netlist \ubaa9\ub85d\uc5d0 \uc6d0\ud558\ub294 \ubaa8\ub4c8\ub4e4\uc774 \uc0ac\ub77c\uc9c0\uc9c0 \uc54a\uace0 \uc81c\ub300\ub85c \ud569\uc131\ub41c \uac83\uc744 \ud655\uc778\ud560 \uc218 \uc788\uc5c8\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Type error<\/h3>\n\n\n\n<h4 class=\"wp-block-heading\">logic type error \ubc1c\uc0dd<\/h4>\n\n\n\n<p>\uc785\uc0ac\ud55c \ub4a4, 2\ubc88\uc9f8 \ud504\ub85c\uc81d\ud2b8\ub97c \uc9c4\ud589\ud560 \ub54c System Verilog \ud30c\uc77c\uc744 \ubc1b\uc544\uc11c FPGA \ud569\uc131\uc744 \uc9c4\ud589\ud558\ub824\uace0 \ud588\uc2b5\ub2c8\ub2e4. System Verilog\ub294 \ud655\uc7a5\uc790\uba85\uc774 .sv\uc778\ub370 \uc800\ud76c \ud68c\uc0ac\ub294 System Verilog\uc5d0 \uc775\uc219\uc9c0\uac00 \uc54a\uc544\uc11c .v\ub85c \uc218\uc815\ud558\uace0 \uc791\uc5c5\uc744 \uc9c4\ud589\ud588\uc5c8\uc5b4\uc694.<\/p>\n\n\n\n<p>RTL integration \uc791\uc5c5\uc774 \ub05d\ub098\uc11c bit \ud30c\uc77c \ud569\uc131\uc744 \ub3cc\ub838\ub294\ub370 \ub2e4\uc74c\uacfc \uac19\uc740 ERROR\uac00 \ubc1c\uc0dd\ud588\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>&#91;Synth 8-993] logic is an unknown type<\/code><\/pre>\n\n\n<style>.kb-image7_496611-bb.kb-image-is-ratio-size, .kb-image7_496611-bb .kb-image-is-ratio-size{max-width:650px;width:100%;}.wp-block-kadence-column > .kt-inside-inner-col > .kb-image7_496611-bb.kb-image-is-ratio-size, .wp-block-kadence-column > .kt-inside-inner-col > .kb-image7_496611-bb .kb-image-is-ratio-size{align-self:unset;}.kb-image7_496611-bb figure{max-width:650px;}.kb-image7_496611-bb .image-is-svg, .kb-image7_496611-bb .image-is-svg img{width:100%;}.kb-image7_496611-bb .kb-image-has-overlay:after{opacity:0.3;}.kb-image7_496611-bb img.kb-img, .kb-image7_496611-bb .kb-img img{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}@media all and (max-width: 767px){.kb-image7_496611-bb.kb-image-is-ratio-size, .kb-image7_496611-bb .kb-image-is-ratio-size{max-width:280px;width:100%;}.kb-image7_496611-bb figure{max-width:280px;}}<\/style>\n<div class=\"wp-block-kadence-image kb-image7_496611-bb\"><figure class=\"aligncenter\"><img decoding=\"async\" src=\"https:\/\/blog.kakaocdn.net\/dn\/cfP4rY\/btsC84DX1r6\/fkVHLcgxBoHRxV0FRszoP1\/img.png\" alt=\"error message\" class=\"kb-img\"\/><figcaption>error message<\/figcaption><\/figure><\/div>\n\n\n\n<p>\uadf8\ub798\uc11c \ubb54\uac00 \ud574\uc11c \ucc3e\uc544\ubd24\ub294\ub370 logic type\uc740 Verilog\uc5d0\uc11c \uc0ac\uc6a9\ud558\uc9c0 \uc54a\ub294 type\uc774\uc5b4\uc11c System Verilog\ub85c \ud655\uc7a5\uc790\ub97c \ubc14\uafd4\uc918\uc57c \ud55c\ub2e4\uace0 \ud569\ub2c8\ub2e4. \uadf8\ub798\uc11c .v\ub97c \uc6d0\ub798 \ud615\ud0dc\uc778 .sv\ub85c \uc218\uc815\ud558\uace0 \ud569\uc131\uc744 \ub3cc\ub9ac\ub2c8 \uc5d0\ub7ec\uac00 \uc0ac\ub77c\uc84c\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Verilog \ud30c\uc77c\uc744 System Verilog \ud30c\uc77c\ub85c \uc778\uc2dd\ud558\uac8c \ub9cc\ub4dc\ub294 \ubc29\ubc95<\/h4>\n\n\n\n<p>\uc55e\uc5d0\uc11c \uc81c\uac00 \ubc1b\uc558\ub358 System Verilog \ud30c\uc77c\uc774 soc.sv\ub77c\uace0 \ud574\ubd05\uc2dc\ub2e4. \uadf8\ub807\ub2e4\uba74 Verilog\ub85c \ubc14\uafbc \ud30c\uc77c\uc740 soc.v\uac00 \ub429\ub2c8\ub2e4.<\/p>\n\n\n\n<p>\uc5ec\ub7ec \uc0ac\ub78c\uc774 \uac19\uc774 \uc791\uc5c5\ud558\ub294 \ud504\ub85c\uc81d\ud2b8\uc5d0\uc11c \uc81c\uac00 FPGA \ud30c\ud2b8\ub97c \ub9e1\uc558\ub294\ub370, \ud569\uc131\uc6a9\uc73c\ub85c soc_fpga.sv \uac19\uc740 \ud30c\uc77c\uc744 \ucd94\uac00\ub85c \uc0dd\uc131\ud55c\ub2e4\uba74 \ubb38\uc81c\uac00 \ubc1c\uc0dd\ud558\uac8c \ub429\ub2c8\ub2e4. \uc218\uc11d\ub2d8\uc774 soc.v\ub97c \uc791\uc5c5\ud558\uc2dc\uba74 \uadf8\ub54c\ub9c8\ub2e4 bit \ud30c\uc77c \ud569\uc131\uc6a9\uc73c\ub85c \ub9cc\ub4e0 soc_fpga.sv\ub97c soc.v\uc5d0 \ub9de\uac8c \uc218\uc815\ud574\uc57c \ud569\ub2c8\ub2e4. \ub108\ubb34 \uadc0\ucc2e\uaca0\uc8e0??<\/p>\n\n\n\n<p>\uc704\uc640 \uac19\uc740 \ubb38\uc81c\ub97c \ud574\uacb0\ud558\uae30 \uc704\ud574 \uba85\ub839\uc5b4\ub85c Verilog \ud30c\uc77c\uc744 System Verilog \ud30c\uc77c\ub85c \uc778\uc2dd\ud558\uac8c \ub9cc\ub4e4 \uc218 \uc788\uc2b5\ub2c8\ub2e4. TCL \ud30c\uc77c\uc5d0 \uc785\ub825\ud558\uba74 \ub3fc\uc694.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>set_property file_type SystemVerilog &#91;get_files &lt;filename&gt;.v]<\/code><\/pre>\n\n\n\n<p>\ub9cc\uc57d \ud30c\uc77c \uc774\ub984\uc774 soc.v\ub77c\uace0 \ud55c\ub2e4\uba74<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>set_property file_type SystemVerilog &#91;get_files soc.v]<\/code><\/pre>\n\n\n\n<p>\uc774\ub807\uac8c \uc791\uc131\ud558\uba74 vivado tool\uc774 Verilog \ud30c\uc77c\uc744 \uc790\ub3d9\uc73c\ub85c System Verilog \ud30c\uc77c\ub85c \uc778\uc2dd\ud569\ub2c8\ub2e4.<\/p>\n\n\n<style>.kadence-column7_513a3b-5f > .kt-inside-inner-col{box-shadow:0px 0px 14px 0px rgba(0, 0, 0, 0.2);}.kadence-column7_513a3b-5f > .kt-inside-inner-col,.kadence-column7_513a3b-5f > .kt-inside-inner-col:before{border-top-left-radius:0px;border-top-right-radius:0px;border-bottom-right-radius:0px;border-bottom-left-radius:0px;}.kadence-column7_513a3b-5f > .kt-inside-inner-col{column-gap:var(--global-kb-gap-sm, 1rem);}.kadence-column7_513a3b-5f > .kt-inside-inner-col{flex-direction:column;}.kadence-column7_513a3b-5f > .kt-inside-inner-col > .aligncenter{width:100%;}.kadence-column7_513a3b-5f > .kt-inside-inner-col:before{opacity:0.3;}.kadence-column7_513a3b-5f{position:relative;}@media all and (max-width: 1024px){.kadence-column7_513a3b-5f > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}@media all and (max-width: 767px){.kadence-column7_513a3b-5f > .kt-inside-inner-col{flex-direction:column;justify-content:center;}}<\/style>\n<div class=\"wp-block-kadence-column kadence-column7_513a3b-5f\"><div class=\"kt-inside-inner-col\">\n<p><strong>\uad00\ub828 \uae00<\/strong><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/fpga-ila-setup-guide\/\">ILA \ubaa8\ub4c8 \uc124\uc815 \ubc0f \uc0ac\uc6a9 \uac00\uc774\ub4dc<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/fpga-dcm-setup-guide\/\">DCM \ubaa8\ub4c8 \uc124\uc815 \ubc0f \uc0ac\uc6a9 \uac00\uc774\ub4dc<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/fpga-block-memory-setup-guide\/\">Block memory \ubaa8\ub4c8 \uc124\uc815 \ubc0f \uc0ac\uc6a9 \uac00\uc774\ub4dc<\/a><\/p>\n\n\n\n<p>\u2705<a href=\"https:\/\/rtlearner.com\/vio-setup-guide\/\">VIO \uc0ac\uc6a9 \uac00\uc774\ub4dc, pin test<\/a><\/p>\n<\/div><\/div>\n\n\n\n<p>\ucc38\uace0: <a href=\"https:\/\/digilent.com\/reference\/programmable-logic\/guides\/vivado-xdc-file\" target=\"_blank\" rel=\"noopener\">XDC file \uc124\uba85<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>To generate bit files for RTL design and FGPA verification, you need to create an xdc file. This article will cover how to write an xdc file.<\/p>","protected":false},"author":1,"featured_media":629,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_kadence_starter_templates_imported_post":true,"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"_kad_post_classname":"","footnotes":""},"categories":[8],"tags":[10,28,35,36],"class_list":["post-7","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-fpga","tag-fpga","tag-semiconductor","tag-xilinx","tag-vivado"],"_links":{"self":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/7","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/comments?post=7"}],"version-history":[{"count":23,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/7\/revisions"}],"predecessor-version":[{"id":1240,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts\/7\/revisions\/1240"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media\/629"}],"wp:attachment":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/media?parent=7"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/categories?post=7"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/tags?post=7"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}<!-- This website is optimized by Airlift. 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