\ubc18\ub3c4\uccb4 \uc124\uacc4\uc5d0\ub294 \ubc18\ub4dc\uc2dc \uc678\ubd80\uc5d0\uc11c \ub4e4\uc5b4\uc624\ub294 clock\uc774 \uc788\uc2b5\ub2c8\ub2e4. \uc774\ub294 FPGA test \uc2dc, \ubcf4\ub4dc\uc5d0 \uc788\ub294 external clock\uc73c\ub85c \uc0ac\uc6a9\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4. \ud558\uc9c0\ub9cc \uc774 clock\uc758 \uc8fc\ud30c\uc218\uac00 \uc720\uc800\uac00 \uc6d0\ud558\ub294 \uac12\uc774 \uc544\ub2d0 \uacbd\uc6b0\uc5d0\ub294 \uc6d0\ud558\ub294 \uc8fc\ud30c\uc218\uc758 clock\uc744 \ub9cc\ub4e4 \ud544\uc694\uac00 \uc788\uc2b5\ub2c8\ub2e4. Clock \ubd84\uc8fc\ub97c \ud1b5\ud574 \ub0ae\uc740 \uc8fc\ud30c\uc218\ub97c \ub9cc\ub4e4 \uc218 \uc788\uc9c0\ub9cc, \ub354 \ube60\ub978 clock\uc774 \ud544\uc694\ud55c \uacbd\uc6b0\uc5d0\ub294 \ubb38\uc81c\uac00 \uc0dd\uae41\ub2c8\ub2e4.<\/p>\n\n\n\n
ASIC \ud658\uacbd\uc5d0\uc11c\ub294 PLL(phase locked loop)\uc744 \uc0ac\uc6a9\ud558\uba74 clock \uc8fc\ud30c\uc218\ub97c \ubc14\uafb8\ub294 \uac83\uc774 \uac00\ub2a5\ud558\uc9c0\ub9cc, FPGA \ud658\uacbd\uc5d0\uc11c\ub294 \ub2e4\ub978 \ubc29\ubc95\uc774 \ud544\uc694\ud569\ub2c8\ub2e4.<\/p>\n\n\n\n
DCM(digital clock manager)\uc740 Vivado\uc5d0\uc11c \uc0dd\uc131\ud560 \uc218 \uc788\ub294 clock generator\ub85c \uc720\uc800\uac00 \uc6d0\ud558\ub294 \uc8fc\ud30c\uc218\uc758 clock\uc744 \uc0dd\uc131\ud560 \uc218 \uc788\uc2b5\ub2c8\ub2e4. \uadf8\ub7ec\uba74 FPGA test\ub97c \uc704\ud55c clock generator\ub294 \uc5b4\ub5bb\uac8c \ub9cc\ub4dc\ub294 \uac83\uc778\uc9c0 \uc54c\uc544\ubcf4\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n