{"id":1071,"date":"2025-12-09T13:57:25","date_gmt":"2025-12-09T04:57:25","guid":{"rendered":"https:\/\/rtlearner.com\/?p=1071"},"modified":"2025-12-12T10:12:33","modified_gmt":"2025-12-12T01:12:33","slug":"rtl-async-fifo-design","status":"publish","type":"post","link":"https:\/\/rtlearner.com\/en\/rtl-async-fifo-design\/","title":{"rendered":"[RTL] Asynchronous FIFO \uc124\uacc4\ud558\uae30"},"content":{"rendered":"\n

\uc9c0\ub09c RTL CDC \uae00\uc744 \ud1b5\ud574 \uc6b0\ub9ac\ub294 \ub2e8\uc77c \ube44\ud2b8(1-bit) \uc2e0\ud638\ub97c \ub3d9\uae30\ud654\ud558\ub294 2-FF Synchronizer\uc640 Multi-bit \uc2e0\ud638\uc758 \uc704\ud5d8\uc131\uc5d0 \ub300\ud574 \ubc30\uc6e0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n\n

\uc774\uc81c CDC \uc774\ub860\uc758 ‘\ub05d\ud310\uc655’\uc774\uc790, SoC \ubc0f FPGA \uc124\uacc4\uc5d0\uc11c \uac00\uc7a5 \ub9ce\uc774 \uc0ac\uc6a9\ub418\ub294 \ube14\ub85d \uc911 \ud558\ub098\uc778 Asynchronous FIFO\ub97c \uc9c1\uc811 \uc124\uacc4\ud574 \ubcfc \ucc28\ub840\uc785\ub2c8\ub2e4. \uc11c\ub85c \ub2e4\ub978 clock domain \uc0ac\uc774\uc5d0\uc11c \ub300\ub7c9\uc758 \ub370\uc774\ud130\ub97c \uc548\uc804\ud558\uac8c \ub118\uae30\uae30 \uc704\ud574 \ubc18\ub4dc\uc2dc \uac70\uccd0\uc57c \ud560 \uad00\ubb38\uc785\ub2c8\ub2e4.<\/p>\n\n\n\n

\ub2e8\uc21c\ud788 \ucf54\ub4dc\ub97c \ubcf5\uc0ac\ud574\uc11c \uc4f0\ub294 \uac83\uc744 \ub118\uc5b4, “\ub3c4\ub300\uccb4 \uc65c \ud3ec\uc778\ud130\ub97c \uadf8\ub808\uc774 \ucf54\ub4dc(Gray Code)\ub85c \ubcc0\ud658\ud574\uc57c \ud558\ub294\uc9c0”<\/strong>, “Full\/Empty \ud50c\ub798\uadf8\ub294 \uc5b4\ub5a4 \uae30\uc900\uc73c\ub85c \ub9cc\ub4e4\uc5b4\uc9c0\ub294\uc9c0”<\/strong> \uadf8 \ub0b4\ubd80 \uc6d0\ub9ac\ub97c \ud30c\ud5e4\uccd0 \ubcf4\uaca0\uc2b5\ub2c8\ub2e4.<\/p>\n\n\n