{"id":39,"count":17,"description":"Verilog \uc124\uba85 \ubc0f \uac15\uc758","link":"https:\/\/rtlearner.com\/en\/rtl-engineer\/verilog\/","name":"Verilog","slug":"verilog","taxonomy":"category","parent":2,"meta":[],"_links":{"self":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/categories\/39","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/categories"}],"about":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/taxonomies\/category"}],"up":[{"embeddable":true,"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/categories\/2"}],"wp:post_type":[{"href":"https:\/\/rtlearner.com\/en\/wp-json\/wp\/v2\/posts?categories=39"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}