When designing an NPU for low-power AI semiconductor edge devices, you often find yourself spending more time fighting the EDA tools than writing actual RTL. Have you ever been absolutely certain your code is perfect, hit the Synthesis button, and watched in horror as the Project Summary reports '0' LUTs and '0' BRAMs used? It’s like magic—the dark kind. Or perhaps during Implementation, Vivado spits out a cryptic error log and crashes completely.
In this article, I’ll share the definitive solutions to two of the most frustrating real-world issues: Defending against Logic Pruning and fixing the infamous Fatal Tool Crashes.
1. Where Did My Logic Go? The Secret of Dangling Logic and Pruning
You carefully instantiated a BRAM, meticulously hooked up your MAC array, and ran synthesis. But the report says RAMB36E2 : 0. The tool autonomously wiped out your hard work.
Why does this happen?
Vivado's synthesis engine is incredibly smart, but also ruthless. To optimize chip Area and Power, it aggressively eliminates any logic that does not eventually connect to a top-level Output Port. If a signal doesn't affect the final output, it is deemed "Dead Code" or "Dangling Logic" and pruned away.
This happens all the time during unit testing when you temporarily disconnect output pins or just want to observe internal signals.
The Solution (Defense Skills):
- The Standard Way: Route all critical internal signals to the Top module's Output Ports. (However, due to pin count limits, this isn't always feasible).
- The dont_touch Attribute: This is a direct command to Vivado: "Do not optimize this module or signal; leave it alone!" Add it right before your declaration:
(* dont_touch = "true" *) logic [31:0] my_important_signal;
(* dont_touch = "true" *) SRAM_bram u_sram_low (...);Caution: Using (* mark_debug = "true" *) will also preserve the logic, but it forces the insertion of an ILA (Integrated Logic Analyzer) core. This can exponentially increase synthesis time or cause tool instability. If preservation is your only goal, stick to dont_touch.
2. Missing XDC Constraints
Imagine you are designing an AI core targeting 150MHz. What happens if you run synthesis without providing a clock timing constraint file (timing_constraints.xdc) because you wanted to save time?
Without an XDC, Vivado assumes "No constraints = Must run at infinite speed," or it simply loses its optimization direction. The tool might exhaust your PC's memory trying to achieve the impossible, crash unexpectedly, or insert random buffers that completely ruin your logic routing.
The Solution: Always create a clock constraint immediately after creating a project.
# Clock Constraint for 150 MHz (1 / 150,000,000 = 6.666... ns)
create_clock -period 6.667 -name sys_clk -waveform {0.000 3.333} [get_ports clk]This single line gives Vivado a clear guideline: "The goal is 6.6ns. As long as signals arrive within this window, don't over-optimize." This dramatically increases tool stability.
3. Could not create slave interpreter / ps_wizard Error
You are running Implementation or Simulation, and the process suddenly halts with errors like:
ERROR: [Common 17-232] Could not create slave interpreter 'rodin:slave19'
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'ps_wizard'
ERROR: [Common 17-3645] Failed to remove file D:/.../.Xil/...
This is never an RTL code issue. It is a zombie process problem caused by a tangled internal Tcl engine or Windows File Locks holding onto temporary files from a previous crashed run. It frequently occurs when Vivado fails while trying to auto-insert Debug Cores (ILA).
3-Step Exorcism (Cache Wipe): Clicking Reset Runs in the GUI will absolutely not fix this. You must manually clean the directory via File Explorer.
- Kill Vivado: Open Task Manager and force close any lingering vivado.exe and tclsh.exe processes.
- Delete the Hidden Root of Evil, the .Xil Folder (Crucial): Go to your project directory and enable "Show hidden files". You will see a folder named .Xil. Shift+Delete this entire folder. The File Locks trapped inside here are the root cause of all these errors.
- Clean the Remnants: Delete the .cache, .hw, .runs, and .sim folders. (Your code is safe in .srcs).
After these 3 steps, reboot your PC. When you restart Vivado, your implementation will finish smoothly as if the errors never existed.
References: AMD
