The need for FPGA testing using VIO
FPGA verification presents numerous challenges due to numerous variables and debugging points. However, board-based verification is a crucial step, as it's virtually the only verification method that allows for real-world verification of performance, previously only confirmed through simulations before the chip is released. Therefore, it's crucial to minimize the number of variables in the test suite.
When something goes wrong with a test, the first thing to check is whether the board pins are functioning normally. If the simulation passes without any problems, but an FPGA test has a problem, I get really excited;; Then I start to suspect this and that, but in my case, the first thing I do is test whether the board pins are functioning normally. This is because a passing simulation means that there are no problems with the RTL design and verification code.
At first, I connected something like a core clock to the IO pin and performed a pin test. Since the core clock continues to run when power is turned on, the pin output toggles continuously as soon as the bit is downloaded. Then, by recording the signal with an oscilloscope and checking it, I was able to confirm that there were no problems with the IO pin.
However, the above method requires bit file synthesis, which inevitably leads to time delays. The VIO module allows for easy pin testing by allowing control from Windows without the need to individually connect core clocks to each pin at the RTL stage.
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Create a project
You can create a project in Vivado and immediately perform FPGA pin testing. First, create a project and select the default options. Then, when selecting the Part (board), the user searches for and selects the board to be tested. I used the VCU118 board.
After creating a project, click Create Block Design in IP INTEGRATOR on the left to create a block design.
Since we'll only be including one module in the Block design, we need to set it to Wrapper. Set Design to Wrapper, then click + in the diagram and search for "vio" to add the module.
Once you've created the VIO module, you'll need to configure its options. You'll need to set the number of probe_in and probe_out pins. Since we only want to look at the pin outputs, set probe_in to 0 and probe_out to the number of pins you want to test. The module diagram will then automatically update.
Once you're done setting up your module options, select all the pins and press Ctrl+t to automatically create pads.
Now, let's input the input clock information. Double-click the automatically generated clk_0 and enter the clock information. When you power on the board, you can automatically input the frequency of the external clock. After that, you can proceed to the implementation.
XDC setting
Once the implementation is complete, the following menu will be activated in the window. You can think of it as the pin settings set in the XDC file. If you set the pin constraint in IO Ports, the xdc settings will be automatically set. After setting the xdc and proceeding with generate bitstream, a bit file will be generated.
The above xdc configuration method has the advantage of allowing you to easily visually check pin settings while proceeding. However, it has the disadvantage of restarting synthesis from the beginning if you change the settings and proceed with bit synthesis. To prevent this, you can set up the xdc file and start synthesis from the beginning when creating the project. This will allow you to complete synthesis more quickly.
Here is an example xdc setting:
set_property PACKAGE_PIN AY14 [get_ports {probe_out0_0[0]}]
set_property PACKAGE_PIN AY15 [get_ports {probe_out1_0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {probe_out0_0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {probe_out1_0[0]}]
set_property PACKAGE_PIN AW15 [get_ports {probe_out2_0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {probe_out2_0[0]}]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]Once bit synthesis is complete, go into Open Hardware Manager and download the generated bit file and the ltx file created to use the module to the board. As with ILA, the ltx file must also be downloaded to the board to use the VIO module properly.
To give you a brief explanation, this is not downloading the RTL-based bit file that designed the chip, but rather downloading the bit file and ltx file synthesized solely for the purpose of pin testing by creating a project with vivado in Windows.
A control window will automatically pop up, allowing you to set the values for each probe. When performing a pin test, simply set the probes to toggle buttons. You'll then see the pin output change with each click.
The above method allows you to control the pin's value (high or low) in a window. Connecting an oscilloscope to the pin and verifying that it operates as intended will allow you to determine whether the pin is functioning properly.
After testing the pins like this, debugging is performed by checking the assign conditions of modules (clock_wiz, block memory, etc.) created for xdc settings or bit file synthesis.
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References: xilinx vio datasheet
