In the previous article, we learned that Post-Simulation (GLS) is essential for ensuring the actual operation of a chip. At the heart of this is the Standard Delay Format (SDF) file, which contains "delay information."
However, when you actually open the SDF file, you can easily get confused because it is full of parentheses and unknown numbers.
In this article, we will dissect the internal structure of the SDF file, which every RTL engineer should be able to read, and analyze from a practical perspective how Corner Case (SS, FF, TT), a core concept in semiconductor verification, is connected to SDF's Min:Typ:Max.
What is an SDF file in RTL design?
SDF is a file format defined by the IEEE standard (IEEE 1497) and is used to transfer accurate delay times (Timing Data) calculated by timing analysis tools (such as PrimeTime) or P&R tools to simulators (such as VCS and Xcelium) or other tools. It is usually provided by design houses.
In simple terms, it's like a report card that contains information like "this gate is 0.5 ns slow, that wiring is 0.2 ns slow."
Basic Structure of SDF
SDF files have a hierarchical structure. They are largely divided into Header, Cell, Delay/Timing Check.
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "my_cpu_top")
(DATE "Dec 05 2024")
(VENDOR "Synopsys")
(PROGRAM "PrimeTime")
(VERSION "K-2015.06")
(DIVIDER /) // Hierarchical separator
(VOLTAGE 1.00:1.00:1.00)
(PROCESS "1.00:1.00:1.00")
(TEMPERATURE 25.00:25.00:25.00)
(TIMESCALE 1ns)
// Information about each instance starts here
(CELL
(CELLTYPE "AND2X1") // Standard Cell name
(INSTANCE u_alu/u_adder/u_and1) // Actual layer path
// 1. Delay information (DELAY)
(DELAY
(ABSOLUTE
// IOPATH: intra-cell delay (input A -> output Y)
(IOPATH A Y (0.050:0.060:0.080) (0.045:0.055:0.075))
// PORT: Delay of the input port itself (mainly used when including wiring delay)
// INTERCONNECT: Wiring delay from another cell output to this cell input
)
)
// 2. Timing Check
(TIMINGCHECK
// SETUP: Based on the rising edge of CK, D must come at least 0.04 ns before
(SETUP D (posedge CK) (0.040:0.040:0.040))
// HOLD: After the rising edge of CK, D must be held for at least 0.01 ns.
(HOLD D (posedge CK) (0.010:0.010:0.010))
)
)
)The most important thing to note here are the numbers that follow (IOPATH A Y ...).
Min:Typ:Max's Secret (The Triplets)
In SDF, latency is always expressed as three values (triplets) in the format Min:Typ:Max.
(0.050 : 0.060 : 0.080)
Min Typ MaxThese numbers represent the performance of the transistor, which varies depending on Process Variation and Operating Condition.
(1) Min (Minimum Delay) – Fastest condition
- Situation: The process is very good (Fast Process), the voltage is high (High Voltage), and the temperature is low (Low Temp -> Inversion layer mobility increases).
- Corner: FF (Fast-Fast) Corner
- Usage: This is primarily used to check for Hold Violation. It checks whether signals arrive too quickly, causing data overwrites.
(2) Max (Maximum Delay) – slowest condition
- Situation: Slow Process, Low Voltage, High Temp.
- Corner: SS (Slow-Slow) Corner
- Usage: This is primarily used to check for Setup Violation. It checks whether signals do not arrive on time, causing data to be lost.
(3) Typ (Typical Delay)
- Situation: Typical process conditions (TT Corner).
- Usage: It's primarily used to gauge performance or predict power consumption. However, since the core of verification is preventing worst-case scenarios (corner cases), it's often less important than Min/Max.
Corner Cases and Simulation Strategies
Beginner designers often think, “Isn’t there just one SDF file that contains all the timings?” However, in reality, you need to create different SDF files depending on your purpose, or select the desired delay values through simulator options.
(1) Which SDF should I select? (STA Tool perspective)
When extracting SDF from STA tool (PrimeTime, etc.), specify a specific Corner (PVT condition).
- Worst-Case SDF: Extracted under SS process, 0.9 V, 125°C conditions. (Max value is very large)
- Best-Case SDF: Extracted under FF process, 1.1 V, -40°C conditions. (Min value is very small)
(2) What values will the simulator read? (Simulator perspective)
Just because the SDF file contains (0.05:0.06:0.08), doesn't mean the simulator will automatically use the values appropriately. You need to specify them as runtime arguments.
+maxdelays: Use the third value (Max) of SDF. -> For Setup Check+mindelays: Use the first value (Min) of SDF. -> For Hold Check+typdelays: Use the middle value (Typ) of SDF.
[Practical Tip] Can't Setup and Hold be done at the same time?
In theory, it is difficult to perfectly verify both Setup and Hold simultaneously in a single simulation run.
- Setup check: Since the delay in signal arrival is the problem, it should be run under Max Delay (SS Corner) conditions. Hold violations are less likely to occur in this case.
- Hold check: The problem is that the signal changes too quickly, so it must be run under Min Delay (FF Corner) conditions.
Therefore, before tape-out, it's essential to perform setup verification with Max Delay SDF, and separately perform hold verification with Min Delay SDF. (Usually, the tool automatically buffers hold during the P&R phase, but it's safer to double-check with GLS.)
SDF Annotation Method ($sdf_annotate)
To load an SDF file in Verilog Testbench, use the $sdf_annotate system task.
module tb_top;
// ... (Testbench code) ...
initial begin
// Load SDF file
// Syntax: $sdf_annotate("file path", target module, configuration file, log file, "MIN/TYP/MAX", scale factor, "FROM_MTM");
`ifdef SDF_MAX
$sdf_annotate("output/design_ss.sdf", u_dut, , "sdf.log", "MAXIMUM");
`elsif SDF_MIN
$sdf_annotate("output/design_ff.sdf", u_dut, , "sdf.log", "MINIMUM");
`endif
end
endmodule- Target module: Instance name of the top-level module to which the SDF will be applied (e.g.
u_dut). - “MAXIMUM” / “MINIMUM”: You can force which position of the SDF Triplet described above will be retrieved. It's usually best to leave this blank and control it with the simulator option (
+maxdelays).
Note
SDF-based gate-level simulation (GLS) is useful for finding timing issues that are not found in RTL simulation by reflecting actual delay information, but it is not a complete timing sign-off tool.
STA (Static Timing Analysis) is mainly responsible for actual product-level timing verification, while GLS is used to supplement verification of specific scenarios such as reset operations, X-propagation, clock-gating, scan/DFT operations, some glitches, and abnormal initialization.
Also, since the delay value is determined by parasitic extraction after layout and library characteristics, SDF itself is just a format, and the delay accuracy depends on the quality of the extraction flow.
Since GLS is vector-based, it cannot 100% cover all combinations of corners, fluctuations (PVT), CDC, meta-stability, and glitches, so it must be used in conjunction with other sign-off flows such as CDC analysis, formal verification, and STA multi-corner analysis.
Understanding and leveraging these constraints makes SDF-based GLS a powerful tool for more deeply verifying the real-world behavior of your designs.
References: chipverify
