In the previous article, we looked at how semiconductor process uncertainty (process variation) changes transistor speed and causes setup/hold time violations in RTL designs.
But here's the question: "The Verilog code I wrote worked perfectly in simulation (pre-sim), so why does it have problems on the actual chip or after synthesis?"
This is because the simulations we normally run are ideal environments. In this article, we'll discuss post-simulation (gate-level simulation), a reality that RTL engineers must face.
Ideal World: RTL Simulation (Pre-Sim)
The first functional simulation we perform when we start designing is called Pre-Sim.
- Zero Delay: If wires A and B are connected, when signal A changes, signal B also changes immediately (0 ns). (Of course, you can provide a delay like #1, but that's a fake delay for verification purposes.)
- Ideal Clock: The clock is a perfect square wave and arrives at all flip-flops simultaneously (Skew = 0).
- Wire: There is no wiring resistance or capacitance. The signal travels instantaneously.
In other words, Pre-Sim is a step to check whether “the logic is correct”, but it does not guarantee whether “the actual circuit will work”.
Real World: Netlists and SDFs
When RTL code undergoes synthesis, it becomes a netlist, a collection of standard cells provided by the foundry, rather than abstract code. Then, through the Place & Route (P&R) process, actual wiring information is generated.
From this point on, ‘physical time’ intervenes.
- Cell Delay: It takes 0.05 ns to pass through one AND gate. (Example)
- Net Delay: The signal takes 0.2 ns to reach the wire due to the long wiring length. (Example)
The file that contains all this delay information is called SDF (Standard Delay Format).
What is Post-Sim (GLS)?
Post-Simulation, or GLS (Gate-Level Simulation), is a simulation that runs by overwriting (back-annotating) the SDF file to the netlist created above.
Now, the simulator operates based on actual gate and wiring delays, not RTL code. This allows for some truly terrifying things to happen that weren't visible in Pre-Sim.
- Unknown signal: If the timing is off and the data is corrupted, it becomes an X (Unknown) state, and this X propagates throughout the entire circuit.
- Glich : In a split second, an unwanted pulse pops out.
- Race Condition: The phenomenon of data arriving earlier or later than the clock is recorded as it is on the waveform.
Why do post-sim?
STA (Static Timing Analysis) tools can check timing, so why bother with the time-consuming Post-Sim process? STA assumes accurate constraints, so it can't detect constraint errors or CDC problems.
(1) X-Propagation (initialization problem)
In RTL, you can give an initial value like reg a = 0;, but in the actual chip (Netlist), you don't know whether the Flip-Flop will be 0 or 1 when the power is turned on. If there is a register that is not initialized due to an error in the reset logic, that part will remain as X (Unknown) in the post-sim and will not work.
(2) Asynchronous circuit (CDC) and multi-cycle path verification
When signals pass between different clock domains (CDC), the STA checks against constraints. If the engineer incorrectly configures set_false_path, the STA passes, but the chip dies. By running GLS with actual latency, you can visually see how the 2-FF Synchronizer resolves the metastability state, or fails to resolve it and returns an x (unknown).
(3) Power Estimation
Accurate power analysis requires information on switching activity (how frequently a signal changes). Power analysis requires GLS results (VCD/FSDB files) that reflect actual glitches and delays, rather than zero-delay RTL simulation results. This allows for accurate predictions of actual chip heat generation and power consumption.
Conclusion: A Bridge from Code to Silicon
If Pre-Sim is the process of checking, “Did I design the RTL as I intended?”, Post-Sim is the process of checking, “Will the chip run well when it comes out of the factory?”
Of course, Post-Sim requires a lot of setup, simulation speed is very slow, and debugging is difficult. However, only after going through this process can we truly say, "The design is complete."
In the following article, we will dissect the SDF file, which is the core of this Post-Sim, and cover practical details on how to set up corner cases (Min/Max) in simulation.
References: chipverify
