[System Verilog] Overview – 2 control flow
You can control the flow of System Verilog with specific conditions or loops.
-
-
[System Verilog] Overview - 1 introduction, data type
System Verilog is a language used in semiconductor design to describe the behavior of hardware.
-
[Verilog] UART RTL design 3
This article concludes the UART RTL design. Related article: ✅[Verilog] Simulation…
-
[Verilog] UART RTL design 2
Continuing from the previous post, let's continue with the UART RTL design. Related posts…
-
[Verilog] UART RTL design 1
This time, we'll design a simple communication IP, a Universal Asynchronous Receiver/Transmitter (UART). Related article…
-
[Verilog] Timer RTL design
This time, let's design a simple timer using the APB interface and counter. Previously…
![[Verilog] UART RTL design 2](data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%20768%201289'%3E%3C/svg%3E)
