[Verilog] FSM (Finite State Machine) RTL Design Principles
모든 디지털 시스템은 크게 데이터를 처리하는 Data Path와 이를 지휘하는…
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[RTL] RTL Arithmetic: Bit Extension, Saturation Operations, and Rounding
When designing RTL, you declare wire [7:0] a, b, c…
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[Verilog] Asynchronous Signal Processing: CDC and Metastability
In the last post, while designing the UART Rx module, I was looking at the asynchronous signal (Rx) coming from the outside…
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[System Verilog] Overview – 4 interface
Verilog에서는 모듈 간 통신을 위해 port를 wire로 연결했습니다. System Verilog에서는…
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[System Verilog] Overview – 3 process, communication
Related article ✅[System Verilog] Overview – 1 introduction, data type…
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[System Verilog] Overview – 2 control flow
You can control the flow of System Verilog with specific conditions or loops.
![[Verilog] 비동기 신호 처리: CDC와 Metastability](data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%20727%20322'%3E%3C/svg%3E)
