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The story of a non-major becoming an RTL engineer
  • 글 설명 이미지, DCM 설명
    FPGA

    [FPGA] DCM module Setup and Usage Guide

    The DCM (digital clock manager) is a clock generator available in Vivado that allows users to generate clocks of any desired frequency. Now, let's explore how to create a clock generator for FPGAs.

  • 글 설명 이미지, ILA 설명
    FPGA

    [FPGA] ILA module Setup and Usage Guide

    ILA is a monitoring module built into Vivado during FPGA synthesis, used to monitor desired signals. So, let's learn how to use it.

  • 글 설명 이미지
    FPGA

    [FPGA] XDC Setup Method and Other Error Solutions

    To generate bit files for RTL design and FGPA verification, you need to create an xdc file. This article will cover how to write an xdc file.

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