[RTL] Correlation Between Process Variation and Setup/Hold Time

As an RTL engineer, when I run synthesis or do STA (Static Timing Analysis), I hear the term PVT (Process, Voltage, Temperature) condition over and over again.

“Did you catch the setup in the worst case?”, “Is the hold okay in the best case?”

Those who only design tend to think of this ‘Process’ as simply an option set in the tool.

In this article, I will explain how process variation threatens design timing by linking two fields.

Ideal and Reality

The code we wrote in Verilog is logically sound, but actually implementing it on a wafer is a different matter.

Numerous variables arise during the semiconductor manufacturing process (eight major processes). These subtle differences are called process variation. Process variation occurs primarily in two areas: the front-end-of-line (FEOL) process, where transistors are manufactured, and the back-end-of-line (BEOL) process, where wiring is connected.

(1) FEOL: Variation in transistor performance

• Photo/Etching (L variation): Due to wavelength limitations of light or uneven flow of etching gas, the gate length of a transistor may be slightly longer or shorter than intended. Gate length is directly related to speed.
• Ion Implantation (Variation of Vth – RDF): A hot topic in recent microfabrication is Random Dopant Fluctuation (RDF). Even a statistically small difference in the number of dopants (impurities) entering the channel region can cause significant fluctuations in the threshold voltage.

(2) BEOL: Variation in wiring delay (RC Delay)

• Deposition & Polishing (CMP): In the CMP process of laying and planarizing metal wiring, depending on the density of the pattern, some areas are eroded more (erosion) and some areas are eroded less (dishing).
• This causes the resistance (R) to change when the cross-sectional area of ​​the metal wiring changes, and the capacitance (C) to change when the insulation thickness changes. In other words, the interconnect delay will be different from what was expected.

Physics: Variation Creates Speed

For RTL engineers, the question is, "So, does this make the transistor faster or slower?" Let's take a very simple look at the MOSFET current equation (saturation region).

A higher current flow means that the capacitor charges quickly, which means faster operation (less delay).

1. Gate Length Reduction: What if the etching is excessive and the channel length becomes shorter? -> Current increases -> Faster speed
2. Threshold Voltage (V_th) decrease: What if the threshold voltage is lowered due to less doping? -> Current increases -> Faster speed

The opposite would mean slow.

Corner Case

In a fab, all chips on a wafer are managed to fall within a Gaussian distribution. However, statistically, chips at either extreme exist. These are called corners.

• Typical-Typical (TT): Average speed for both NMOS and PMOS (most ideal)
• SS (Slow-Slow): When both NMOS and PMOS are made slowly due to process variables.
• FF (Fast-Fast): When both NMOS and PMOS are made quickly due to process variables.

RTL Timing: Setup vs. Hold

Now let's see how this physical phenomenon is captured in our Timing Report.

(1) SS Corner -> Setup Time Violation

Due to a manufacturing issue, transistors are made slowly. It takes too long for data to travel from one flip-flop to the next through combinational logic.

• Phenomenon: The clock has arrived but the data has not yet arrived.
• Result: Setup Time ViolationThe chip will not work unless you lower the operating frequency.

(2) FF Corner -> Hold Time Violation

Due to a process issue, the transistors are too fast. Data is passed to the next flip-flop too quickly.

• Phenomenon: Before the data that should be caught in the current clock can be caught, the next data is overwritten.
• Result: Hold Time Violation. This is a Critical Failure. Lowering the frequency does not solve the timing problem, so a hold fix process such as inserting a buffer is required.

Conclusion: The Role of Engineers

This is why we provide margins in our synthesis tools (e.g. Design Compiler).

• RTL designers must secure setup margin by reducing logic depth to allow operation even at SS Corner.
• At the same time, we need to defend the Hold Margin through buffers and other means to prevent data from leaking out too quickly in FF Corner.

Understanding the imperfections of semiconductor processes helps us understand why we impose such tight timing constraints. Ultimately, design and process are engaged in an invisible tug-of-war to produce a good chip (yield).

References: anysilicon