RTL design engineer work

During my master's degree, I conducted research on semiconductor processes and devices, but then switched careers and joined a fabless company, where I'm currently working as an RTL design engineer. I'd like to briefly describe the work I've done during my career.

I will continue to update.

RTL design engineer OJT

Study

I joined the company in early February 2023 and spent the first month studying. I studied semiconductor design flow, CPU operation, bus architecture, memory, and peripherals, and started writing Verilog in early March.

My first assignment was to write a testbench for an I2C controller and run a simulation, but I ran into problems right from the start. Seriously, I didn't even know C, let alone Verilog, and I'd never even used Linux. And now I'm suddenly being asked to write a testbench and run a simulation?

First of all, the reason I use Linux is because I need to design RTL code in Verilog and synthesize it using EDA tools from Synopsys or Cadence. However, since these tools are all Linux-based, I also need to do the RTL code on Linux. So, when I get to work and turn on my computer, I open a program called VNC Viewer and connect to the company server computer to work. (Actually, I can work from home, too.)

The story was long, but anyway, the first task was a testbench and simulation for the I2C controller. While doing so, I was given the RTL code for the I2C controller.

‘It works in both Master and Slave modes, so connect them by attaching APB BFM to each

load data from a file, and test the data loop back.’

I was really moved to tears…

Testbench

Create a checklist

To verify a module, you must first create a checklist.

It's listed in the I2C standard, and it says it supports Standard-mode, Fast-mode, and Fast-mode Plus. The module has a register that sets the timing, so I need to check if it's working properly as I've set it.

You can set it to Master mode, Slave mode, and you need to check the 7-bit / 10-bit address mode (I don't know about DMA yet, so I'll skip it...). And you need to check whether the default values ​​of the module registers are read properly, and if they are writeable, whether the values ​​are set as entered.

Finally, I finished the checklist with the Data Loop back test, which was my homework.

Block diagram

Once you've decided what tests to perform, you need to draw a block diagram. At first, I didn't understand why I needed to draw one, but I definitely noticed that drawing the diagram and then starting to code reduced my errors. In the integration section I'll discuss later, drawing this block diagram well is incredibly important.

RTL design

So, I should really start doing RTL design in Verilog, right? I still don't know much about it, but back then, I knew nothing about the syntax, so I received a lot of help from ChatGPT. While it couldn't do all the coding for me, it did write basic scripts for certain functions. For more information on Verilog syntax, please refer to this separate article.

To reiterate, RTL design is conducted in a Linux environment. We use tools from Synopsys or Cadence to design and synthesize, and these tools run on Linux. So, when I arrive at the office, I turn on my computer and use a remote program called VNC Viewer to connect to the company server computer and work. I use CentOS for Linux, so you can expect to rarely use Windows.

RTL Simulation

The purpose of a testbench is to verify the functionality of a module designed in RTL. Therefore, simulations and waveforms must be verified using the checklist described above.

When I first tested the I2C controller module, it took me two weeks, but after that, it got faster and faster, so I was able to finish testing in one week for the UART and one week for the GPIO/PIT combined.

Time table recommendation, XLGantt

When I started my on-the-job training, my manager gave me an Excel file and told me to use it as a timetable. It's so convenient and has so many great features, I'm writing this to recommend it.

Excel Gantt is a macro program, so it doesn't require separate installation. It's saved as an .xlsm file, so you can use it right away.

Enter the task name, the start date in the yellow section, and the end date in the green section. A schedule will automatically be generated, as shown in the red box. Enter the task's progress percentage in the orange section, and the red box will automatically update.

I've given a brief explanation, but for more detailed information, please refer to the ExcelWorks website.

SoC integration

From then on, I participated in one of the company's projects and did a simple task: integration.

While some companies, like ARM, develop their own IP, our company designs SoC platforms at the request of our clients. We purchase IP that meets the specifications of the chip being designed and then design it into a chip. We'll cover the semiconductor design flow separately later.

So, if I show you a little bit of what I worked on, it's very simple.

The AHB and APB buses are connected by a bridge, and each APB bus has various peripherals attached. I was in charge of the APB0 portion, and the RTL design itself wasn't difficult. All I had to do was instantiate several modules and connect them properly.

However, the difficult part was that since many people were working together, we had to follow the coding rules, so to speak. Although they didn't affect the compilation, we had to follow the internally established rules. That makes collaboration easier and looks better. However, since our company was relatively new, we hadn't yet established our own rules. So, even after completing the integration, if the senior manager said that another method would be better and changed the rules, we had to go through the hassle of having to change everything one by one;;;

I'll show you how my coding style changed after I established the coding style and rules when I first wrote the testbench.

It's not a big deal, but it's definitely easier to see after the change, right? I think the reason is because it's aligned well. Another coding rule is signal name setting. When naming the APB signal above, let's take the I2C and APB0 'pwrite' signal as an example.

You need to set it as pwrite_i2c / pwrite_apb0 and connect the two through assign.

assign  pwrite_i2c  =  pwrite_apb0;

But if you go back and forth between whether to set it to i2c_pwrite or pwrite_i2c, you have to edit, edit, edit, edit, edit every time (I simply integrated it, but the script was over 4000 lines, almost 5000 lines. You have to find and change every part that needs to be edited.)

Another annoying thing is that I can't use tabs. Everyone has different spacing settings for tabs (mine is 2 spaces), but they said that if I use tabs, the alignment will be all wrong for other people, so they don't let me use them and tell me to use 4 spaces. So when I edit, I keep repeating 'delete + space bar 4 times'. It's really simple labor;;;

Juniors will likely need to develop good coding habits to suit the company's style early on.

FPGA test

Semiconductor design goes through multiple stages of verification, verification, and re-verification. After a program or app is developed and released, if an error is discovered, it can be fixed and updated. However, once a semiconductor is created and fabricated, RTL modifications are not possible until a set quantity is produced at a foundry like TSMC. There are no updates!!

So, we verify functionality through RTL simulation and conduct FPGA testing to ensure proper operation in the real world. FPGAs are a separate topic, but simply put, they are semiconductors that can be modified.

Data sheet

RTL design engineers, especially those working at fabless SoC companies, are inevitably exposed to data sheets. Data sheets are essentially user manuals containing detailed information about the IP. They provide invaluable information on specifications (features, block diagrams, input/output signals, functions, etc.) and register descriptions.

My job involved overall FPGA component design and IP design. After IP RTL design, I created a data sheet, which required me to record IP information in great detail. This allowed the software team to review register descriptions and properly write testcase code (verification code).

Drawing a timing diagram

Drawing with Excel

When creating a data sheet, you may need to draw a timing diagram. Initially, I used Excel's border function to draw the timing diagram.

As shown in the image above, the cell dividers prevent you from using the image as a photograph. In this case, you can remove the dividers in Excel's options.

1. First, go to Excel Options
2. Select the Advanced tab
3. Select the sheet for which you want to remove grid lines
4. You just need to turn off the gridlines.

Drawing with Wavedrom

However, drawing timing diagrams in Excel can be cumbersome, wavedrommakes it easy. There's no installer; simply download and run the exe file. The diagram is created by writing code. There's a tutorial on the website for your reference.

References: The Role of the RTL Engineer