To verify the RTL design on a board, you need to generate a bit file. To do this, you must create an xdc file. This constraint file is essential for verification as it optimizes the board's operation and ensures it works correctly.
In this article, we will look at how to write constraints for board testing.
XDC(Xilinx Design Constraint) Explanation
The XDC file is a design constraint file used in the Vivado tool, allowing you to configure various constraints for tests using the board. Representative constraints configured in this file include clock constraints, pin settings, and pull-up/down settings.
Clock constraint
When designing a chip, there are clocks coming in as inputs. You need to either add an oscillator to the board to generate the clock, or set constraints for the incoming clock when connecting a JTAG for debugging.
create_clock -period 50.000 -name clock1 -waveform {0.000 25.000} [get_ports input_port]
The red textis what the user needs to configure. Set the clock's period and name, and then enter the name of the input port where the clock comes in from the actual RTL code. So, in the RTL-designed chip_top, the clock coming into the input_port pin has a period of 50nsand is named clock1.
2. Pin Setting (Pin Mapping)
There are several IO pins on the FPGA board. Of course, we need to connect the inputs and outputs of chip_top to the FPGA's IO pins, right? To do that, we first need to look at the data sheet of the board we are using and figure out the pin map.
For example, if you want to connect an inout called GPIO0 in the RTL top to a pin called A0 on the board (as shown in the data sheet),
set_property PACKAGE_PIN A0 [get_ports GPIO0]
You can write it like this.
Next, set the voltage of the pin. Most of the time, 3.3V or 1.8V is used.
set_property IOSTANDARD LVCMOS33 [get_ports GPIO0]
When it's 3.3V, write LVCMOS33, and when it's 1.8V, write LVCMOS18.
pull up/down Setting
Finally, set the pull-up and pull-down. If you want to use a communication IP such as I2C or SPI, you should set it to pull-up, right??
set_property PULLUP true [get_ports GPIO0]
Troubleshooting other errors
DONT TOUCH
Problem
I received the System Verilog file, ran FPGA synthesis, and tested it. However, errors kept occurring, and it seemed like one module was missing;; So I checked the source list, and I confirmed that the modules that were properly imported in the source were not in the netlist list after synthesis. I don't know why, but it seemed like the Vivado tool completely blew it during the synthesis process;;
Solved with DONT_TOUCH
There is a way to prevent the Vivado tool from blowing up a module, it is called DONT_TOUCH, you can see an example by following the Link.
(* DONT_TOUCH = "yes" *) //DONT_TOUCH
module example_dt_ver
(clk,
In1,
In2,
out1);The method is to input (* DONT_TOUCH = “yes” *) above the module declaration at the very top of the RTL code. By performing the above processing, I was able to confirm that the desired modules were properly synthesized and did not disappear from the synthesized netlist list after synthesis.
Type error
logic type error
After joining the company, I was working on my second project and wanted to receive a System Verilog file and perform FPGA synthesis. System Verilog has an .sv extension, but since our company wasn't familiar with it, I modified it to .v and proceeded with the work.
After completing the RTL integration task and running the bit file synthesis, the following ERROR occurred.
[Synth 8-993] logic is an unknown type
So I did some research and it seems that logic type is not used in Verilog, so I need to change the extension to System Verilog. So I changed .v to its original format, .sv, and ran the synthesis, and the error went away.
How to make Verilog files recognized as System Verilog files
Let's say the System Verilog file I received earlier is called soc.sv. Then, the file converted to Verilog would be soc.v.
I'm in charge of the FPGA part of a project where several people are working on it. If I create an additional file like soc_fpga.sv for synthesis, a problem arises. Whenever the senior manager works on soc.v, I have to modify the soc_fpga.sv file, which was created for bit file synthesis, to match the soc.v file. It's a huge hassle, right?
To solve the above problem, you can use a command to make the Verilog file recognized as a System Verilog file. You can do this by entering it into a TCL file.
set_property file_type SystemVerilog [get_files <filename>.v]If the file name is soc.v
set_property file_type SystemVerilog [get_files soc.v]If you write it like this, the vivado tool will automatically recognize the Verilog file as a System Verilog file.
References: XDC file explanation
