[FPGA] DCM module Setup and Usage Guide

Semiconductor design inevitably involves an external clock. This can be used as an external clock on the board during FPGA testing. However, if this clock's frequency is not the desired frequency, a clock of the desired frequency must be created. While clock division can be used to achieve lower frequencies, problems arise when a faster clock is required.

In an ASIC environment, it is possible to change the clock frequency using a PLL (phase locked loop), but in an FPGA environment, a different method is required.

The DCM (digital clock manager) is a clock generator available in Vivado that allows users to create clocks of any frequency they desire. Now, let's explore how to create a clock generator for FPGA testing.

How to create a DCM

First, select IP Catalog from the Project manager on the far left of the Vivado window.

When you select IP Catalog, a window like the following will appear. Search for wiz and select the corresponding module.

Then, a window will appear where you can set the module's options. I will explain the values ​​you need to change one by one.

Set options

First, you need to check the Component Name in the red box. So, when instantiating this Name, make sure you enter it correctly.

Next, check Phase Alignment and enter the Input Clock information in the blue box. Most boards use an external clock, so enter the appropriate information. Let's take a look at the next page.

2nd page

The next page is where you enter information about the clock output. Here, you only need to specify the number of output clocks, their frequency, and the reset type. If you set two clk_outs and the reset type to "Active low," the diagram will automatically change.

Instantiation

After creating a module in Vivado, you can add the module by writing the following code in RTL.

clk_wiz_0 u_PLL0 (
    .clk_in1    (ext_clk),
    .clk_out1   (clk_40M),
    .clk_out2   (clk_20M),
    .locked     ()
);

Here, ext_clk is the external source clock, and clk_40M and clk_20M are the names of the user-defined clocks. Since I set 40MHz and 20MHz as output, I named them clk_40M and clk_20M for easy identification.

참조: Xilinx DCM datasheet