About AMBA
AMBA (Advanced Microcontroller Bus Architecture) is a bus protocol developed by ARM. There are several types, but most commonly use the APB, AHB, and AXI buses. Buses are the conduits through which signals are exchanged between chip modules, but why are they categorized this way? That's because each module has different performance characteristics.
For example, if a high-performance CPU and slow-speed DRAM or peripherals are connected to a single bus, the bus will remain busy as data processing slows down. The CPU or other high-performance modules will then have to wait until all bus signals are processed.
So, high-performance modules are connected to high-performance buses, and relatively low-performance modules are connected to low-performance buses to optimize the performance of the entire system.
You can see that high-performance modules are connected to the AHB bus, and low-performance modules, such as UART, are connected to the bus, and the two buses are connected by a bridge. The bus performance is higher in the order of AXI > AHB > APB.
Now, let’s take a look at the buses above one by one.
APB bus
As its name suggests, the Advanced Peripheral Bus is a bus for peripherals. It simplifies the interface, resulting in lower cost and lower power consumption.
If you look at the block diagram, you will see several signals. Let's look at the specification and analyze them one by one.
Signals
For more detailed information on Signals, please refer to the description. Let's understand the protocol by looking at a transfer example.
Basic transfer
Write transfer with no wait states
This is an example of a write transfer. Basically, data is transferred from the clock position, and I'll explain it section by section.
- T1 – T2 : Addr 1 is loaded into PADDR. Transferring to this address is performed, and PWRITE is high, indicating a write transfer. The slave is selected with the PSEL signal, but the master has not yet set PENABLE. Therefore, although the data is loaded, it is not passed to the slave.
- T2 – T3 : When PENABLE goes high and the slave is ready to receive data, it sends a PREADY high signal. Then, data transfer occurs at clock posedge T3.
Here is an example when the Slave is not ready to receive data.
Write transfer with wait states
From T2 – T3, PREADY is low, which means the slave is not ready to receive data. So, we can see that other signals are waiting until PREADY becomes high.
Slave was ready at T4 - T5, so transfer occurred at T5.
Read transfer with no wait states
Next is a read transfer. The difference from a write transfer is that PWRITE is low and data is exchanged using PRDATA rather than PWDATA. If you understand write transfers, this won't be difficult. Finally, I'll conclude this article with an example involving a wait state.
Read transfer with wait states
The wait state occurs when the PREADY signal is low, meaning the slave is not ready to transfer. However, in practice, the PREADY signal is often tied high.
So, you can see that there is no wait state in this bus protocol. (Because it is such a simple bus.)
Slave error signal
If the slave encounters an error during communication for any reason, it signals this via the PSLVERR signal. PSLVERR is meaningful only in the last cycle of a transfer, at which time PSEL, PENABLE, and PREADY must be high.
Well, let's finish explaining the protocol by looking at an example timing diagram.
Write transfer with slave error signal
Read transfer with slave error signal
However, in practice, since the PSLVERR signal is also tied low, you can consider the slave response signal to be only PRDATA.
References: ARM® AMBA APB Protocol Specification
