While the APB bus prioritized optimization over performance, as it was intended for modules that didn't require high performance, such as peripherals, the AHB (Advanced High-performance Bus) is a bus focused more on performance. As such, it has more signals and its actual operation is more complex.
Well then, let’s take a closer look at the specifications.
Block diagram
Let's start with the block diagram, shall we? At first glance, it appears to be a simple structure: the Master selects multiple Slaves via HSEL and exchanges data via HWDATA and HRDATA. However, there are several signals and functions not found on the APB bus. Let's take a look at the signals.
Signals
Spec. Ch 2 describes the signal.
First, just like the APB bus, there's a clock and an active low resetn. This is where things get crazy...
Master signals
I understand HADDR,,,, but what about the rest?? It's not over yet, lol
Except for HWDATA and HWRITE, these are the signals I don't know,,, These are the signals coming from the Master.
Slave signals
HRDATA would be the data going from Slave to Master,,,, HREADYOUT means Slave ready status, right?? There are so many unknown signals, so let's find out by checking the actual AHB operation one by one.
AHB Read / Write
Single transfer
Spec. Ch. 3 describes Transfer. Let's first look at Basic Transfer.
Looking at the timing diagram above, it doesn't seem to be much different from the APB transfer, but unlike the APB transfer, it's divided into an address phase and a data phase. Let's take a quick look at the APB transfer timing diagram.
In the case of APB transfer, when the slave is ready to receive data and PREADY is displayed, the slave receives the data, and during this time, the PADDR continues to hold the signal. However, in the case of AHB transfer, because the address and data phases are separated, the HADDR does not need to continuously hold the signal. So what is the advantage of this? Let's understand it by looking at multiple transfers.
Multiple transfer
First, let's look at the scenario of the transfer above. If write is 1, it's a write, and if it's 0, it's a read, right?? It writes to address A, reads data from address B, and writes to address C, but when reading data from address B, the slave is not ready for what's happening, so it waits for 1 clock cycle and proceeds.
One of the characteristics of multiple transfer is that the address phase and data phase overlap.
By overlapping the data phase and the address phase of the next transfer, multiple transfers can be performed continuously, thereby improving performance.
Burst mode transfer
HTRANS[1:0] description
HTRANS[1:0] indicates the status of the transfer.
- 00(IDLE) : Transfer is not in progress via bus
- 01(BUSY) : The master cannot proceed with the next transfer for some reason.
- 10(NONSEQ) : If there was no previous transfer and this is the first transfer, then it is a single transfer, then it is NONSEQ.
- 11(SEQ) : Status in progress following the previous transfer
Here's an example of a transfer type. Let's take a closer look. All transfers are reads, since HWRITE is low.
The HBURST[2:0] signal will be explained a little later.
- T0 – T1 : This is the address phase of the first transfer. Since this is the first transfer, HTRANS is in the NONSEQ state.
- T1 – T2 : The data phase of address 0X20 and the address phase of 0X24 are overlapping. From the second transfer onwards, it is in SEQ state, but the Master is not ready to process the next transfer, so it is in BUSY state. The 0X20 data was received, but the address phase of the next transfer, 0X24, will have to come out once more.
- T2 – T3 : You can see that the BUSY state has ended and moved to the SEQ state. After that, you can see that the SEQ state is maintained until the transfer is finished. This is the 0X24 address phase.
- T3 – T4 : This is a situation where the 0X24 data phase and the 0X28 address phase overlap.
- T4 – T5 : The transfer is not in progress because the slave is not ready to send data. Since HREADY LOW is present at T5 clock posedge, it waits until both address and data are HREADY HIGH.
- T5 – T6 : The 0X28 data phase and the 0X2C address phase are overlapping.
- T6 – T7 : 0X2C data phase. The last data is read from the slave.
HMASTLOCK Description
The above example only performed one transfer to one address. But what if you need to perform two transfers?
The HMASTLOCK signal allows multiple transfers to be performed to a single address. The example above is a transfer that reads and immediately writes data from address A. Since the HMASTLOCK signal is high, you can see that the A address phase is continuously displayed and data is read and written. Also, since HTRANS is NONSEQ, there was no previous transfer, and if the first transfer was NONSEQ, the second transfer is also to the same address due to HMASTLOCK – High, so you can see that it is in NONSEQ state.
HBURST[2:0] Description
Now, let's learn about Burst mode, which is the core of the AHB Bus. AHB Burst mode can be controlled with the HBURST[2:0] and HSIZE[2:0] signals.
Remember in the previous figure, the HBURST signal was INCR? If you understand the description in the table above, you'll probably understand the HBURST signal.
Single is obviously a single transfer, and there are 4-, 8-, and 16-beat bursts, where "beat" refers to the number of data to be transferred. For example, a 16-beat burst means that 16 data pieces are transferred consecutively. An undefined length burst means that the number of data to be transferred is not specified. Now, let's learn about INCR and WRAP.
Incrementing burst
Incrementing burst mode is a mode that transfers by continuously increasing the address. The amount of increase can be set using the HSIZE[2:0] signal.
Wrapping burst
Wrapping burst mode does not continuously increase the address like incrementing burst mode, but creates a boundary and increases the address only within that boundary. The boundary can be set through HBURST and HSIZE.
HSIZE[2:0] Description
The HSIZE[2:0] signal indicates the size of the data transfer. Let's look at an example to understand how the transfer varies depending on the HBURST and HSIZE signals mentioned above.
Burst examples
Incrementing burst example
First, incrementing burst mode. Now, you can understand everything except HPROT, right? You can check the status through HTRANS. It is a read transfer, and you can see that HREADY is low from T1 to T2, so it waits for 1 clock cycle.
Since HBURST[2:0] is INCR4, the address increases without boundary when reading 4 data,
Since HSIZE[2:0] is a word (4-byte), you can see that the addresses start at 0X38 and increase by 4 to 0X3c, 0X40, and 0X44.
This time, since it is INCR8, we will transfer 8 pieces of data. Since the word is a halfword, you can see that the address increases by 2 bytes.
Wrapping burst example
In wrapping burst, we need to calculate the boundary. Since it is a 4-beat burst and a word (4-byte), we can see that the boundary is 4*4 = 16 (0X10). Therefore, we can see that it does not go from 0X3C to 0X40, but returns to 0X30.
This is an 8-beat wrapping burst. Let's calculate from the boundary. 8-beat * word (4-byte) = 32 (0x20). So the address goes from 0X3C to 0X20.
Undefined burst example
Finally, there's Undefined length burst mode. Setting it to Undefined length burst allows you to transfer up to three data sets.
Slave response signals
The Slave responds to the transfer by the Master via the HRESP signal, and there are two states: OKAY and ERROR.
- 0 (OKAY) : Transfer completed successfully
- 1 (ERROR) : There was an error in the transfer
So, you can check the status of the transfer through the Slave source signals HRESP and HREADYOUT.
The important thing about HRESP is that the ERROR signal must be sent for more than two clock cycles.
Let's understand by looking at the timing diagram above.
- T0 – T1 : A's address phase is successfully transferred to the slave (HREADYOUT 1, HRESP 0 – Successful transfer completed)
- T1 – T2 : Slave sends wait status (0,0 – Transfer pending)
- T2 – T3 : Slave sends ERROR signal (0,1 – ERROR response, first cycle)
- T3 – T4 : Slave is out of wait state and ready to proceed with transfer (1,1 – ERROR response, second cycle)
- T4 – T5 : Slave sends OKAY signal (1,0 – Successful transfer completed)
The slave cancels the address already loaded on the bus by sending an ERROR signal twice.
Arbitration
I think we can conclude the article on the AHB bus with a discussion of arbitration.
HBUSREQ: A signal from the Master to the Arbiter requesting use of the bus.
HLOCK: This is a signal to the Arbiter asking it not to disconnect the bus as the Master is still using it.
HGRANT: The Arbiter sends High to the Master with the highest priority.
HMASTER: Displays the Master currently using the bus.
HMASTLOCK: Indicates that the Master is currently performing a locked sequence.
HSPLIT: Informs the Slave that it can split transactions again.
References: ARM® AMBA 5 AHB Protocol Specification
