As we explored in the previous post (Systolic Array), while powerful Processing Elements (PEs) are essential, the primary concern for a system architect is: "How can we supply data seamlessly and cost-effectively?"
The Von Neumann architecture, the origin of modern computing, separates the 'Processing Unit (CPU)' from the 'Storage Unit (Memory)'.
In the previous post, we quantitatively confirmed that hardware performance limits ...
In our previous posts, we discussed the two main culprits degrading deep learning model performance:
In the previous MLP and Memory Wall, we discussed the "memory wall" phenomenon, where memory bandwidth limits system performance. In CNN and Locality,
In the previous 3 Mappings of Conv Operations, we looked at a strategy to sacrifice memory and gain computational speed (GEMM) through the Im2Col method when processing standard convolutions in hardware.
