[RTL] Multi-Vt and Doping: Same Gate, Different Speeds

When an RTL engineer analyzes the synthesis results, he or she may find that the same AND2 gate has a subtly different name.

• AND2_X1_HVT
• AND2_X1_RVT (or SVT)
• AND2_X1_LVT

Why are they categorized so differently when the functions are the same? If you've only known them as "fast" and "slow," it's time to understand "how these are created within the process." This is the starting point for power-performance optimization.

In this article, we will learn how Multi-Vt (multiple threshold voltage) technology is implemented in a process (Doping) and why it is linked to Leakage Power, a headache for RTL engineers.

1. What is Multi-Vt?

The voltage at which a transistor turns on to act as a switch is called the threshold voltage (V_th). Modern process libraries offer multiple versions of standard cells with different V_th, even within a single process node (e.g., 5nm).

• HVT (High V_th): High threshold. Difficult to turn on (slow). However, less power is leaked when off (low leakage).
• RVT (Regular/Standard V_th): standard.
• LVT (Low V_th): Low threshold. Easy to turn on (fast). However, it leaks electricity even when turned off (high leakage).

RTL engineers mix and match these cells to fit the needs of the application.

2. Role of the process engineer: Controlling doping concentration

So how do process engineers change the V_thof identical transistors, but with different gate thicknesses?

The most basic and cheapest method is to control the doping concentration in the channel region.

Principle: Channel Doping

For a transistor to turn on, electrons (in NMOS) must gather in the channel region below the gate to create a path.

• How to make HVT:
  • Inject more P-type dopant (Boron, etc.) into the channel region (Heavy Doping).
  • When electrons try to pass through, there are many obstacles, so a stronger voltage must be applied to the gate to barely open the path -> V_th rising
• How to make LVT:
  • The doping concentration in the channel region is kept low (light doping).
  • Since there are few obstacles, the path will open quickly even with a small voltage applied. -> V_th descent

💡 Process TMI:

To achieve this, multiple masks are used in the ‘Ion Implantation’ stage of the process, with more ions being fired into the HVT area and less into the LVT area.

3. The RTL Engineer's Dilemma: Speed ​​vs. Leakage

You might think, "So, why don't we just use the fastest LVT?" But this is where the laws of physics come into play.

1) Performance ∝ (V_dd – V_th)

Let's compare a transistor to a faucet.

• LVT: The faucet is loose, so even if you turn it slightly, water (current, I) gushes out. -> Fast action speed.

2) Leakage ∝ 10^-V_th

The problem is when the faucet is turned off.

• LVT: Even when locked, water drops continue to drip. This is called Sub-threshold Leakage.
• HVT: It's locked tightly so there's hardly any water leaking out.

The shocking fact is that even a slight decrease in V_thcauses the leakage current to increase exponentially.

While LVT is 20-30% faster than HVT, its leakage current can be 10-100 times greater. If the entire chip is coated with LVT, the battery will melt and the chip will overheat, even if it's left idle.

4. Practical Guide: How Does a Synthesis Tool Work?

When a synthesis tool (such as Design Compiler) converts the Verilog code written by an RTL engineer, it strategically places these Multi-Vt cells.

1. Initial state: First of all, to save power, most of them are mapped to HVT.
2. Timing Analysis: Timing analysis shows that a specific path (Critical Path) is too slow to match the clock cycle (Setup Violation).
3. Optimization: Only the cells in the path where timing is critical are replaced with LVT.
4. Result: 90% of the chip is HVT/RVT to save power, and only the 10% that are really urgent use LVT to match performance.

The Role of an RTL Engineer

If you stack deep if-else loops or cram complex operations into a single clock (high logic depth), the synthesis tool will use a lot of LVT to keep the timing right.

• Result: Leakage explosion
• Solution: By improving the RTL structure (pipelining) to reduce the logic depth, the tool can again use HVT, resulting in a low-power chip.

5. Summary and Conclusion

1. Multi-Vtis created by controlling the channel doping concentrationof the transistor.
2. LVTis fast, but it's like a leaky faucet when it's off.
3. HVTis a slow, but excellent power-saving device that holds onto electricity.
4. Good RTL design (proper pipelining) helps synthesis tools make extensive use of HVT, ultimately resulting in cool chips.

Now, if a synthesis report shows LVT coating, I hope you'll become an engineer who can see down to the process level, not just say, "That must be fast," but also, "The doping concentration is low, so current is leaking. My code must be tight on timing."

References: wikipedia