[FPGA] Solving Timing Violations: False Path and Multicycle Path

I ran Implementationin Vivado, and a red number appeared in the Design Timing Summaryshowing a negative WNS (Worst Negative Slack).

At this point, FPGA engineers often wonder, "Is there something wrong with the design?" and try to fix the code. However, in most cases like this, the problem lies in the Constraints files. This is because the error may have occurred because the system was trying to force a path that physically cannot be reached within one clock cycle.

In this article, we'll explain the correct setup and precautions for False Pathand Multicycle Path, two of the most powerful methods for eliminating timing errors.

1. Why are Timing Constraints Necessary?

Vivado's Static Timing Analyzer (STA) basically assumes that "data transmission between all registers must be completed within 1 clock cycle."

However, exceptions exist in real circuits.

1. CDC (Clock Domain Crossing): Timing cannot be met between different clocks. (Impossible to check)
2. Slow Signals: What if you use a 100MHz clock, but a specific control signal changes only once every 2-3 clocks? There is no need to push it to arrive within 1 clock.

If you do not specify these exceptions in the xdc (Xilinx Design Constraints) file, the Vivado tool spits out a Timing Violationwhile trying to solve an impossible homework assignment.

2. False Path: "Do Not Check This Path"

False Pathis a command that completely excludesa path from timing analysis.

2.1. When to Use?

• CDC (Clock Domain Crossing): clk_A domain to clk_B domain crossing signal. (Must be handled at the circuit level with a 2-FF Synchronizer, etc.)
• Asynchronous Reset: A path from an asynchronous reset pin to a register.
• Configuration Signals: Mode setting pins that are set once at boot and do not change.

2.2. XDC command syntax (Tcl)

This is the most used pattern. You can enter it in the Vivado Tcl Console or in an xdc file.

① Breaking the relationship between clocks (most common)

# clk_a에서 clk_b로 가는 모든 경로는 무시해라
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]

# 반대 방향도 무시 (양방향 CDC인 경우)
set_false_path -from [get_clocks clk_b] -to [get_clocks clk_a]

# Ignore all paths from clk_a to clk_b
set_multicycle_path -from [get_clocks clk_a] -to [get_clocks clk_b]

# Ignore the opposite direction (if it's bidirectional CDC)
set_multicycle_path -from [get_clocks clk_b] -to [get_clocks clk_a]

② Ignore specific pins (Reset, etc.)

# 'sys_rst_n' 포트에서 시작되는 모든 경로는 무시
set_false_path -from [get_ports sys_rst_n]

# Ignore all paths starting from 'sys_rst_n' port
set_multicycle_path -from [get_ports sys_rst_n]

⚠️ Caution: set_multicycle_pathis very powerful. If you accidentally place this on a valid data path, the tool will abandon timing checks and place it arbitrarily. This will result in the worst-case scenario: random chip malfunctions.Be sure to apply this only where the CDC circuit (synchronizer) is present.

3. Multicycle Path: "Take Your Time"

Multicycle Pathallows data to take more than one clock cycle (N Cycles) to arrive.

3.1. When to use?

• Enable-based logic: If a 100MHz clock is used, but the enable signal turns on once every 4 clocks, data is transferred.
• Complex arithmetic operations: such as multiplication or division, where the combinational circuit delay is large and cannot be calculated within 1 clock, but the result can be obtained 2-3 clocks later through pipeline design.

3.2. Key Pitfall: Hold Time (N-1 Rule)

This is a senior's know-how.Many people simply increase the setup and feel secure, but then a Hold Violationoccurs.

• Default behavior: Setup checks are performed at cycle 1 (default), and Hold checks are performed at cycle 0 (on the same edge).
• Setup is increased to 2: The tool will attempt to send data as slowly as possible, as it has more setup time.
• Problem: Data may start too late, potentially violating the Hold check threshold (cycle 0).
• Solution: If Setup is increased to N, the Hold check threshold must also be pushed back by N-1.

3.3. XDC command syntax (Tcl)

Setup N cycles, Hold N-1 cycles

For example, let's assume the path from cpu_coreto mem_ctrlhas 3 clocks of headroom.

# 1. Setup을 3주기로 완화 (기본값 1 -> 3)
set_multicycle_path -setup 3 -from [get_pins cpu_core/reg_out] -to [get_pins mem_ctrl/reg_in]

# 2. Hold를 2주기(3-1) 뒤로 이동 (필수!)
set_multicycle_path -hold 2 -from [get_pins cpu_core/reg_out] -to [get_pins mem_ctrl/reg_in]

# 1. Relax the setup to 3 cycles (default 1 -> 3)
xdc -setup 3 -from [get_pins cpu_core/reg_out] -to [get_pins mem_ctrl/reg_in]

#2. Move Hold back 2 cycles (3-1) (Required!)
xdc -hold 2 -from [get_pins cpu_core/reg_out] -to [get_pins mem_ctrl/reg_in]

💡 Summary formula:

• Setup = N
• Hold = N – 1

4. Practical Guide: The Order of Application in Vivado

This is the flow for reporting timing errors and writing constraints.

1. Check Timing Report:
   • After Vivado Implementation is complete, Open Implemented Design.
   • Report Timing Summary Click.
   • Intra-Clock Paths error? -> Logic is too long. (Need to add pipeline or consider Multicycle)
   • Inter-Clock Paths error? -> 99% probability it's CDC. (Consider False Path)
2. Path Analysis:
   • Double-click the Failing Path to view its Path Properties.
   • Make sure the Start Point and End Point are in different clock domains.
   • Check theSchematicto see if there's a synchronizer (2-FF) in the middle.
3. Create XDC:
   • If it's safe to do so, add the set_false_path or set_multicycle_path commands described above to the xdcfile.
4. Re-run:
   • Rerun the implementation. Verify that the WNS value has changed to positive.

5. Conclusion: Constraints Are Not Magic

When a timing error occurs, novice engineers inevitably want to eliminate it by implementing a False Path. This is like driving blindfolded.

1. Is the circuit safe? (Check CDC processing)
2. Is the slowness truly acceptable? (Check design intent)

Constraints should only be used when these two factors are confirmed. Correctly applied constraints are the ultimate tool for accelerating your workday.

References: xilinx